6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-05 13:26:55 +00:00
Code Issues Projects Releases Wiki Activity

ARM VREV64df and VREV64qf can just be patterns. The instruction is the same

Browse Source 
as for VREV64d32 and VREV64q32, respectively.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127485 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-03-11 20:18:05 +00:00
parent f0112a224f
commit 1558df79b4
2 changed files with 2 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
utils/TableGen/ARMDecoderEmitter.cpp
View File

@@ -1654,13 +1654,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
Name == "VEXTq16" || Name == "VEXTq32" || Name == "VEXTqf")
return false;
// Vector Reverse is similar to Vector Extract. There is no distinction
// between data types, other than size.
//
// VREV64df is equivalent to VREV64d32.
// VREV64qf is equivalent to VREV64q32.
if (Name == "VREV64df" || Name == "VREV64qf") return false;
// VDUPLNfd is equivalent to VDUPLN32d.
// VDUPLNfq is equivalent to VDUPLN32q.
// VLD1df is equivalent to VLD1d32.