mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Revert 69952. Causes testsuite failures on linux x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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f6b9f260ed
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@ -353,13 +353,6 @@ public:
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SDValue getConvertRndSat(MVT VT, DebugLoc dl, SDValue Val, SDValue DTy,
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SDValue STy,
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SDValue Rnd, SDValue Sat, ISD::CvtCode Code);
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/// getVectorShuffle - Return an ISD::VECTOR_SHUFFLE node. The number of
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/// elements in VT, which must be a vector type, must match the number of
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/// mask elements NumElts. A negative integer mask element is treated as
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/// undefined.
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SDValue getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1, SDValue N2,
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const int *MaskElts);
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/// getZeroExtendInReg - Return the expression required to zero extend the Op
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/// value assuming it was the smaller SrcTy value.
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@ -1703,32 +1703,6 @@ public:
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}
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};
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class ShuffleVectorSDNode : public SDNode {
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SDUse Ops[2];
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int *Mask;
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protected:
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friend class SelectionDAG;
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ShuffleVectorSDNode(MVT VT, DebugLoc dl, SDValue N1, SDValue N2, int *M)
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: SDNode(ISD::VECTOR_SHUFFLE, dl, getSDVTList(VT)), Mask(M) {
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InitOperands(Ops, N1, N2);
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}
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public:
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const int * getMask() const { return Mask; }
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bool isSplat() { return isSplatMask(Mask, getValueType(0)); }
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int getSplatIndex() {
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assert(isSplat() && "Cannot get splat index for non-splat!");
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return Mask[0];
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}
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static bool isSplatMask(const int *Mask, MVT VT);
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static bool classof(const ShuffleVectorSDNode *) { return true; }
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static bool classof(const SDNode *N) {
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return N->getOpcode() == ISD::VECTOR_SHUFFLE;
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}
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};
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class ConstantSDNode : public SDNode {
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const ConstantInt *Value;
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friend class SelectionDAG;
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@ -2110,7 +2084,7 @@ public:
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return N->getOpcode() == ISD::CONDCODE;
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}
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};
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/// CvtRndSatSDNode - NOTE: avoid using this node as this may disappear in the
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/// future and most targets don't support it.
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class CvtRndSatSDNode : public SDNode {
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@ -328,7 +328,7 @@ public:
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/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
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/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
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/// are assumed to be legal.
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virtual bool isShuffleMaskLegal(const int *Mask, MVT VT) const {
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virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const {
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return true;
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}
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@ -336,7 +336,9 @@ public:
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/// used by Targets can use this to indicate if there is a suitable
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/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
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/// pool entry.
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virtual bool isVectorClearMaskLegal(const int *Mask, MVT VT) const {
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virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
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MVT EVT,
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SelectionDAG &DAG) const {
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return false;
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}
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@ -51,6 +51,15 @@ class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
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int BigOperandNum = BigOp;
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}
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/// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
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/// vector types, and that ThisOp is the result of
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/// MVT::getIntVectorWithNumElements with the number of elements
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/// that ThisOp has.
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class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
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: SDTypeConstraint<ThisOp> {
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int OtherOpNum = OtherOp;
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}
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/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
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/// type as the element type of OtherOp, which is a vector type.
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class SDTCisEltOfVec<int ThisOp, int OtherOp>
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@ -166,8 +175,8 @@ def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
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SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
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]>;
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def SDTVecShuffle : SDTypeProfile<1, 2, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
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def SDTVecShuffle : SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
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]>;
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def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
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SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
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@ -5098,21 +5098,7 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
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return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
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InVec.getValueType(), &Ops[0], Ops.size());
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}
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// If the invec is an UNDEF and if EltNo is a constant, create a new
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// BUILD_VECTOR with undef elements and the inserted element.
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if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF &&
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isa<ConstantSDNode>(EltNo)) {
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MVT VT = InVec.getValueType();
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MVT EVT = VT.getVectorElementType();
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unsigned NElts = VT.getVectorNumElements();
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SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT));
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unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
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if (Elt < Ops.size())
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Ops[Elt] = InVal;
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return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
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InVec.getValueType(), &Ops[0], Ops.size());
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}
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return SDValue();
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}
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@ -5174,8 +5160,9 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
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// to examine the mask.
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if (BCNumEltsChanged)
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return SDValue();
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int Idx = cast<ShuffleVectorSDNode>(InVec)->getMask()[Elt];
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int NumElems = InVec.getValueType().getVectorNumElements();
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unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2).
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getOperand(Elt))->getZExtValue();
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unsigned NumElems = InVec.getOperand(2).getNumOperands();
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InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
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if (InVec.getOpcode() == ISD::BIT_CONVERT)
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InVec = InVec.getOperand(0);
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@ -5222,6 +5209,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
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SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
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unsigned NumInScalars = N->getNumOperands();
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MVT VT = N->getValueType(0);
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unsigned NumElts = VT.getVectorNumElements();
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MVT EltType = VT.getVectorElementType();
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// Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
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@ -5264,36 +5252,56 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
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}
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// If everything is good, we can make a shuffle operation.
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MVT IndexVT = MVT::i32;
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if (VecIn1.getNode()) {
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SmallVector<int, 8> Mask;
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SmallVector<SDValue, 8> BuildVecIndices;
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for (unsigned i = 0; i != NumInScalars; ++i) {
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if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
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Mask.push_back(-1);
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BuildVecIndices.push_back(DAG.getUNDEF(IndexVT));
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continue;
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}
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// If extracting from the first vector, just use the index directly.
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SDValue Extract = N->getOperand(i);
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// If extracting from the first vector, just use the index directly.
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SDValue ExtVal = Extract.getOperand(1);
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if (Extract.getOperand(0) == VecIn1) {
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Mask.push_back(cast<ConstantSDNode>(ExtVal)->getZExtValue());
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if (ExtVal.getValueType() == IndexVT)
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BuildVecIndices.push_back(ExtVal);
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else {
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unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
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BuildVecIndices.push_back(DAG.getConstant(Idx, IndexVT));
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}
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continue;
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}
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// Otherwise, use InIdx + VecSize
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unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
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Mask.push_back(Idx+NumInScalars);
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BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, IndexVT));
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}
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// Add count and size info.
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if (!TLI.isTypeLegal(VT) && LegalTypes)
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MVT BuildVecVT = MVT::getVectorVT(IndexVT, NumElts);
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if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes)
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return SDValue();
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// Return the new VECTOR_SHUFFLE node.
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SDValue Ops[2];
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SDValue Ops[5];
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Ops[0] = VecIn1;
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Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
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return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
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if (VecIn2.getNode()) {
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Ops[1] = VecIn2;
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} else {
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// Use an undef build_vector as input for the second operand.
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std::vector<SDValue> UnOps(NumInScalars,
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DAG.getUNDEF(EltType));
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Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
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&UnOps[0], UnOps.size());
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AddToWorkList(Ops[1].getNode());
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}
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Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), BuildVecVT,
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&BuildVecIndices[0], BuildVecIndices.size());
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return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), VT, Ops, 3);
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}
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return SDValue();
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@ -5313,10 +5321,8 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
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}
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SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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return SDValue();
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MVT VT = N->getValueType(0);
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unsigned NumElts = VT.getVectorNumElements();
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SDValue ShufMask = N->getOperand(2);
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unsigned NumElts = ShufMask.getNumOperands();
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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@ -5324,13 +5330,60 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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assert(N0.getValueType().getVectorNumElements() == NumElts &&
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"Vector shuffle must be normalized in DAG");
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// FIXME: implement canonicalizations from DAG.getVectorShuffle()
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// If the shuffle mask is an identity operation on the LHS, return the LHS.
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bool isIdentity = true;
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for (unsigned i = 0; i != NumElts; ++i) {
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if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
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cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) {
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isIdentity = false;
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break;
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}
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}
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if (isIdentity) return N->getOperand(0);
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// If the shuffle mask is an identity operation on the RHS, return the RHS.
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isIdentity = true;
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for (unsigned i = 0; i != NumElts; ++i) {
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if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
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cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() !=
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i+NumElts) {
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isIdentity = false;
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break;
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}
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}
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if (isIdentity) return N->getOperand(1);
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// Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
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// needed at all.
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bool isUnary = true;
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bool isSplat = true;
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int VecNum = -1;
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unsigned BaseIdx = 0;
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for (unsigned i = 0; i != NumElts; ++i)
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if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
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unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue();
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int V = (Idx < NumElts) ? 0 : 1;
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if (VecNum == -1) {
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VecNum = V;
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BaseIdx = Idx;
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} else {
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if (BaseIdx != Idx)
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isSplat = false;
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if (VecNum != V) {
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isUnary = false;
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break;
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}
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}
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}
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// Normalize unary shuffle so the RHS is undef.
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if (isUnary && VecNum == 1)
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std::swap(N0, N1);
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// If it is a splat, check if the argument vector is a build_vector with
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// all scalar elements the same.
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if (cast<ShuffleVectorSDNode>(N)->isSplat()) {
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if (isSplat) {
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SDNode *V = N0.getNode();
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// If this is a bit convert that changes the element type of the vector but
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// not the number of vector elements, look through it. Be careful not to
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@ -5344,7 +5397,6 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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if (V->getOpcode() == ISD::BUILD_VECTOR) {
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unsigned NumElems = V->getNumOperands();
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unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex();
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if (NumElems > BaseIdx) {
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SDValue Base;
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bool AllSame = true;
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@ -5369,6 +5421,38 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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}
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}
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}
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// If it is a unary or the LHS and the RHS are the same node, turn the RHS
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// into an undef.
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if (isUnary || N0 == N1) {
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// Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
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// first operand.
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SmallVector<SDValue, 8> MappedOps;
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for (unsigned i = 0; i != NumElts; ++i) {
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if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
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cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() <
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NumElts) {
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MappedOps.push_back(ShufMask.getOperand(i));
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} else {
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unsigned NewIdx =
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cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() -
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NumElts;
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MappedOps.push_back(DAG.getConstant(NewIdx,
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ShufMask.getOperand(i).getValueType()));
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}
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}
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ShufMask = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
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ShufMask.getValueType(),
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&MappedOps[0], MappedOps.size());
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AddToWorkList(ShufMask.getNode());
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return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(),
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N->getValueType(0), N0,
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DAG.getUNDEF(N->getValueType(0)),
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ShufMask);
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}
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return SDValue();
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}
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@ -5377,42 +5461,52 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
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/// vector_shuffle V, Zero, <0, 4, 2, 4>
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SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
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MVT VT = N->getValueType(0);
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DebugLoc dl = N->getDebugLoc();
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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if (N->getOpcode() == ISD::AND) {
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if (RHS.getOpcode() == ISD::BIT_CONVERT)
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RHS = RHS.getOperand(0);
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if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
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SmallVector<int, 8> Indices;
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unsigned NumElts = RHS.getNumOperands();
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std::vector<SDValue> IdxOps;
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unsigned NumOps = RHS.getNumOperands();
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unsigned NumElts = NumOps;
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for (unsigned i = 0; i != NumElts; ++i) {
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SDValue Elt = RHS.getOperand(i);
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if (!isa<ConstantSDNode>(Elt))
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return SDValue();
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else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
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Indices.push_back(i);
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IdxOps.push_back(DAG.getIntPtrConstant(i));
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else if (cast<ConstantSDNode>(Elt)->isNullValue())
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Indices.push_back(NumElts);
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IdxOps.push_back(DAG.getIntPtrConstant(NumElts));
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else
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return SDValue();
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}
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// Let's see if the target supports this vector_shuffle.
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MVT RVT = RHS.getValueType();
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if (!TLI.isVectorClearMaskLegal(&Indices[0], RVT))
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if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG))
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return SDValue();
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// Return the new VECTOR_SHUFFLE node.
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MVT EVT = RVT.getVectorElementType();
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SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
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DAG.getConstant(0, EVT));
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SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
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RVT, &ZeroOps[0], ZeroOps.size());
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LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS);
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SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
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return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf);
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MVT EVT = RHS.getValueType().getVectorElementType();
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MVT VT = MVT::getVectorVT(EVT, NumElts);
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MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts);
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std::vector<SDValue> Ops;
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LHS = DAG.getNode(ISD::BIT_CONVERT, LHS.getDebugLoc(), VT, LHS);
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Ops.push_back(LHS);
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AddToWorkList(LHS.getNode());
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std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT));
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Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
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VT, &ZeroOps[0], ZeroOps.size()));
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Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
|
||||
MaskVT, &IdxOps[0], IdxOps.size()));
|
||||
SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(),
|
||||
VT, &Ops[0], Ops.size());
|
||||
|
||||
if (VT != N->getValueType(0))
|
||||
Result = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
|
||||
N->getValueType(0), Result);
|
||||
|
||||
return Result;
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -267,10 +267,16 @@ private:
|
||||
bool isVolatile, SDValue ValOp,
|
||||
unsigned StWidth, DebugLoc dl);
|
||||
|
||||
/// promoteShuffle - Promote a shuffle mask of a vector VT to perform the
|
||||
/// same shuffle on a vector of NVT. Must not create an illegal shuffle mask.
|
||||
SDValue promoteShuffle(MVT NVT, MVT VT, DebugLoc dl, SDValue N1, SDValue N2,
|
||||
const int *Mask) const;
|
||||
/// isShuffleLegal - Return non-null if a vector shuffle is legal with the
|
||||
/// specified mask and type. Targets can specify exactly which masks they
|
||||
/// support and the code generator is tasked with not creating illegal masks.
|
||||
///
|
||||
/// Note that this will also return true for shuffles that are promoted to a
|
||||
/// different type.
|
||||
///
|
||||
/// If this is a legal shuffle, this method returns the (possibly promoted)
|
||||
/// build_vector Mask. If it's not a legal shuffle, it returns null.
|
||||
SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
|
||||
|
||||
bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
|
||||
SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
|
||||
@ -313,35 +319,50 @@ private:
|
||||
};
|
||||
}
|
||||
|
||||
/// promoteShuffle - Promote a shuffle mask of a vector VT to perform the
|
||||
/// same shuffle on a vector of NVT. Must not create an illegal shuffle mask.
|
||||
/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
|
||||
SDValue SelectionDAGLegalize::promoteShuffle(MVT NVT, MVT VT, DebugLoc dl,
|
||||
SDValue N1, SDValue N2,
|
||||
const int *Mask) const {
|
||||
MVT EltVT = NVT.getVectorElementType();
|
||||
int NumMaskElts = VT.getVectorNumElements();
|
||||
int NumDestElts = NVT.getVectorNumElements();
|
||||
unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
|
||||
/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
|
||||
/// specified mask and type. Targets can specify exactly which masks they
|
||||
/// support and the code generator is tasked with not creating illegal masks.
|
||||
///
|
||||
/// Note that this will also return true for shuffles that are promoted to a
|
||||
/// different type.
|
||||
SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
|
||||
switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
|
||||
default: return 0;
|
||||
case TargetLowering::Legal:
|
||||
case TargetLowering::Custom:
|
||||
break;
|
||||
case TargetLowering::Promote: {
|
||||
// If this is promoted to a different type, convert the shuffle mask and
|
||||
// ask if it is legal in the promoted type!
|
||||
MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
|
||||
MVT EltVT = NVT.getVectorElementType();
|
||||
|
||||
assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
|
||||
|
||||
if (NumEltsGrowth == 1)
|
||||
return DAG.getVectorShuffle(NVT, dl, N1, N2, Mask);
|
||||
|
||||
SmallVector<int, 8> NewMask;
|
||||
for (int i = 0; i != NumMaskElts; ++i) {
|
||||
int Idx = Mask[i];
|
||||
for (unsigned j = 0; j != NumEltsGrowth; ++j) {
|
||||
if (Idx < 0)
|
||||
NewMask.push_back(-1);
|
||||
else
|
||||
NewMask.push_back(Idx * NumEltsGrowth + j);
|
||||
// If we changed # elements, change the shuffle mask.
|
||||
unsigned NumEltsGrowth =
|
||||
NVT.getVectorNumElements() / VT.getVectorNumElements();
|
||||
assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
|
||||
if (NumEltsGrowth > 1) {
|
||||
// Renumber the elements.
|
||||
SmallVector<SDValue, 8> Ops;
|
||||
for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
|
||||
SDValue InOp = Mask.getOperand(i);
|
||||
for (unsigned j = 0; j != NumEltsGrowth; ++j) {
|
||||
if (InOp.getOpcode() == ISD::UNDEF)
|
||||
Ops.push_back(DAG.getUNDEF(EltVT));
|
||||
else {
|
||||
unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
|
||||
Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
|
||||
}
|
||||
}
|
||||
}
|
||||
Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getDebugLoc(),
|
||||
NVT, &Ops[0], Ops.size());
|
||||
}
|
||||
VT = NVT;
|
||||
break;
|
||||
}
|
||||
assert((int)NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
|
||||
assert(TLI.isShuffleMaskLegal(&Mask[0], NVT) && "Shuffle not legal?");
|
||||
return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
|
||||
}
|
||||
return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
|
||||
}
|
||||
|
||||
SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
|
||||
@ -1631,15 +1652,25 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
|
||||
Tmp1.getValueType(), Tmp2);
|
||||
|
||||
unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
|
||||
MVT ShufMaskVT =
|
||||
MVT::getIntVectorWithNumElements(NumElts);
|
||||
MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
|
||||
|
||||
// We generate a shuffle of InVec and ScVec, so the shuffle mask
|
||||
// should be 0,1,2,3,4,5... with the appropriate element replaced with
|
||||
// elt 0 of the RHS.
|
||||
SmallVector<int, 8> ShufOps;
|
||||
for (unsigned i = 0; i != NumElts; ++i)
|
||||
ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
|
||||
|
||||
Result = DAG.getVectorShuffle(Tmp1.getValueType(), dl, Tmp1, ScVec,
|
||||
&ShufOps[0]);
|
||||
SmallVector<SDValue, 8> ShufOps;
|
||||
for (unsigned i = 0; i != NumElts; ++i) {
|
||||
if (i != InsertPos->getZExtValue())
|
||||
ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
|
||||
else
|
||||
ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
|
||||
}
|
||||
SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, ShufMaskVT,
|
||||
&ShufOps[0], ShufOps.size());
|
||||
|
||||
Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Tmp1.getValueType(),
|
||||
Tmp1, ScVec, ShufMask);
|
||||
Result = LegalizeOp(Result);
|
||||
break;
|
||||
}
|
||||
@ -1677,14 +1708,13 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
|
||||
case ISD::VECTOR_SHUFFLE:
|
||||
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
|
||||
Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
|
||||
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
|
||||
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
|
||||
|
||||
// Allow targets to custom lower the SHUFFLEs they support.
|
||||
switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, Result.getValueType())){
|
||||
default: assert(0 && "Unknown operation action!");
|
||||
case TargetLowering::Legal:
|
||||
assert(TLI.isShuffleMaskLegal(cast<ShuffleVectorSDNode>(Node)->getMask(),
|
||||
Result.getValueType()) &&
|
||||
assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
|
||||
"vector shuffle should not be created if not legal!");
|
||||
break;
|
||||
case TargetLowering::Custom:
|
||||
@ -1698,21 +1728,23 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
|
||||
MVT VT = Node->getValueType(0);
|
||||
MVT EltVT = VT.getVectorElementType();
|
||||
MVT PtrVT = TLI.getPointerTy();
|
||||
const int *Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
|
||||
int NumElems = VT.getVectorNumElements();
|
||||
SDValue Mask = Node->getOperand(2);
|
||||
unsigned NumElems = Mask.getNumOperands();
|
||||
SmallVector<SDValue, 8> Ops;
|
||||
for (int i = 0; i != NumElems; ++i) {
|
||||
if (Mask[i] < 0) {
|
||||
for (unsigned i = 0; i != NumElems; ++i) {
|
||||
SDValue Arg = Mask.getOperand(i);
|
||||
if (Arg.getOpcode() == ISD::UNDEF) {
|
||||
Ops.push_back(DAG.getUNDEF(EltVT));
|
||||
continue;
|
||||
} else {
|
||||
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
|
||||
unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
|
||||
if (Idx < NumElems)
|
||||
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1,
|
||||
DAG.getConstant(Idx, PtrVT)));
|
||||
else
|
||||
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2,
|
||||
DAG.getConstant(Idx - NumElems, PtrVT)));
|
||||
}
|
||||
int Idx = Mask[i];
|
||||
if (Idx < NumElems)
|
||||
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1,
|
||||
DAG.getConstant(Idx, PtrVT)));
|
||||
else
|
||||
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2,
|
||||
DAG.getConstant(Idx - NumElems, PtrVT)));
|
||||
}
|
||||
Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
|
||||
break;
|
||||
@ -1727,8 +1759,9 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
|
||||
Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
|
||||
|
||||
// Convert the shuffle mask to the right # elements.
|
||||
Result = promoteShuffle(NVT, OVT, dl, Tmp1, Tmp2,
|
||||
cast<ShuffleVectorSDNode>(Node)->getMask());
|
||||
Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
|
||||
assert(Tmp3.getNode() && "Shuffle not legal?");
|
||||
Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NVT, Tmp1, Tmp2, Tmp3);
|
||||
Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
|
||||
break;
|
||||
}
|
||||
@ -5457,7 +5490,6 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
|
||||
|
||||
// FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
|
||||
// and use a bitmask instead of a list of elements.
|
||||
// FIXME: this doesn't treat <0, u, 0, u> for example, as a splat.
|
||||
std::map<SDValue, std::vector<unsigned> > Values;
|
||||
Values[SplatValue].push_back(0);
|
||||
bool isConstant = true;
|
||||
@ -5514,17 +5546,21 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
|
||||
|
||||
if (SplatValue.getNode()) { // Splat of one value?
|
||||
// Build the shuffle constant vector: <0, 0, 0, 0>
|
||||
SmallVector<int, 8> ZeroVec(NumElems, 0);
|
||||
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
|
||||
SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
|
||||
std::vector<SDValue> ZeroVec(NumElems, Zero);
|
||||
SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
|
||||
&ZeroVec[0], ZeroVec.size());
|
||||
|
||||
// If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
|
||||
if (TLI.isShuffleMaskLegal(&ZeroVec[0], Node->getValueType(0))) {
|
||||
if (isShuffleLegal(VT, SplatMask)) {
|
||||
// Get the splatted value into the low element of a vector register.
|
||||
SDValue LowValVec =
|
||||
DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, SplatValue);
|
||||
|
||||
// Return shuffle(LowValVec, undef, <0,0,0,0>)
|
||||
return DAG.getVectorShuffle(VT, dl, LowValVec, DAG.getUNDEF(VT),
|
||||
&ZeroVec[0]);
|
||||
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, LowValVec,
|
||||
DAG.getUNDEF(VT), SplatMask);
|
||||
}
|
||||
}
|
||||
|
||||
@ -5546,25 +5582,35 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
|
||||
std::swap(Val1, Val2);
|
||||
|
||||
// Build the shuffle constant vector: e.g. <0, 4, 0, 4>
|
||||
SmallVector<int, 8> ShuffleMask(NumElems, -1);
|
||||
MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
|
||||
MVT MaskEltVT = MaskVT.getVectorElementType();
|
||||
std::vector<SDValue> MaskVec(NumElems);
|
||||
|
||||
// Set elements of the shuffle mask for Val1.
|
||||
std::vector<unsigned> &Val1Elts = Values[Val1];
|
||||
for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
|
||||
ShuffleMask[Val1Elts[i]] = 0;
|
||||
MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
|
||||
|
||||
// Set elements of the shuffle mask for Val2.
|
||||
std::vector<unsigned> &Val2Elts = Values[Val2];
|
||||
for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
|
||||
if (Val2.getOpcode() != ISD::UNDEF)
|
||||
ShuffleMask[Val2Elts[i]] = NumElems;
|
||||
MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
|
||||
else
|
||||
MaskVec[Val2Elts[i]] = DAG.getUNDEF(MaskEltVT);
|
||||
|
||||
SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
|
||||
&MaskVec[0], MaskVec.size());
|
||||
|
||||
// If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
|
||||
if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, VT) &&
|
||||
TLI.isShuffleMaskLegal(&ShuffleMask[0], VT)) {
|
||||
isShuffleLegal(VT, ShuffleMask)) {
|
||||
Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val1);
|
||||
Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val2);
|
||||
return DAG.getVectorShuffle(VT, dl, Val1, Val2, &ShuffleMask[0]);
|
||||
SDValue Ops[] = { Val1, Val2, ShuffleMask };
|
||||
|
||||
// Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
|
||||
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, Ops, 3);
|
||||
}
|
||||
}
|
||||
|
||||
@ -8020,19 +8066,36 @@ SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
|
||||
case ISD::VECTOR_SHUFFLE: {
|
||||
SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
|
||||
SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
|
||||
const int *Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
|
||||
SmallVector<int, 8> NewMask;
|
||||
// VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
|
||||
// used as permutation array. We build the vector here instead of widening
|
||||
// because we don't want to legalize and have it turned to something else.
|
||||
SDValue PermOp = Node->getOperand(2);
|
||||
SDValueVector NewOps;
|
||||
MVT PVT = PermOp.getValueType().getVectorElementType();
|
||||
for (unsigned i = 0; i < NumElts; ++i) {
|
||||
int Idx = Mask[i];
|
||||
if (Idx < (int)NumElts)
|
||||
NewMask.push_back(Idx);
|
||||
else
|
||||
NewMask.push_back(Idx + NewNumElts - NumElts);
|
||||
if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
|
||||
NewOps.push_back(PermOp.getOperand(i));
|
||||
} else {
|
||||
unsigned Idx =
|
||||
cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
|
||||
if (Idx < NumElts) {
|
||||
NewOps.push_back(PermOp.getOperand(i));
|
||||
}
|
||||
else {
|
||||
NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
|
||||
PermOp.getOperand(i).getValueType()));
|
||||
}
|
||||
}
|
||||
}
|
||||
for (unsigned i = NumElts; i < NewNumElts; ++i)
|
||||
NewMask.push_back(-1);
|
||||
|
||||
Result = DAG.getVectorShuffle(WidenVT, dl, Tmp1, Tmp2, &NewMask[0]);
|
||||
for (unsigned i = NumElts; i < NewNumElts; ++i) {
|
||||
NewOps.push_back(DAG.getUNDEF(PVT));
|
||||
}
|
||||
|
||||
SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, dl,
|
||||
MVT::getVectorVT(PVT, NewOps.size()),
|
||||
&NewOps[0], NewOps.size());
|
||||
|
||||
Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, Tmp1, Tmp2, Tmp3);
|
||||
break;
|
||||
}
|
||||
case ISD::LOAD: {
|
||||
|
@ -772,8 +772,10 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
|
||||
// If Lo or Hi uses elements from at most two of the four input vectors, then
|
||||
// express it as a vector shuffle of those two inputs. Otherwise extract the
|
||||
// input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
|
||||
const int *Mask = cast<ShuffleVectorSDNode>(N)->getMask();
|
||||
SmallVector<int, 16> Ops;
|
||||
SDValue Mask = N->getOperand(2);
|
||||
MVT IdxVT = Mask.getValueType().getVectorElementType();
|
||||
SmallVector<SDValue, 16> Ops;
|
||||
Ops.reserve(NewElts);
|
||||
for (unsigned High = 0; High < 2; ++High) {
|
||||
SDValue &Output = High ? Hi : Lo;
|
||||
|
||||
@ -785,15 +787,18 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
|
||||
unsigned FirstMaskIdx = High * NewElts;
|
||||
bool useBuildVector = false;
|
||||
for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
|
||||
SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
|
||||
|
||||
// The mask element. This indexes into the input.
|
||||
int Idx = Mask[FirstMaskIdx + MaskOffset];
|
||||
unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
|
||||
-1U : cast<ConstantSDNode>(Arg)->getZExtValue();
|
||||
|
||||
// The input vector this mask element indexes into.
|
||||
unsigned Input = (unsigned)Idx / NewElts;
|
||||
unsigned Input = Idx / NewElts;
|
||||
|
||||
if (Input >= array_lengthof(Inputs)) {
|
||||
// The mask element does not index into any input vector.
|
||||
Ops.push_back(-1);
|
||||
Ops.push_back(DAG.getUNDEF(IdxVT));
|
||||
continue;
|
||||
}
|
||||
|
||||
@ -821,24 +826,27 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
|
||||
}
|
||||
|
||||
// Add the mask index for the new shuffle vector.
|
||||
Ops.push_back(Idx + OpNo * NewElts);
|
||||
Ops.push_back(DAG.getConstant(Idx + OpNo * NewElts, IdxVT));
|
||||
}
|
||||
|
||||
if (useBuildVector) {
|
||||
MVT EltVT = NewVT.getVectorElementType();
|
||||
SmallVector<SDValue, 16> SVOps;
|
||||
Ops.clear();
|
||||
|
||||
// Extract the input elements by hand.
|
||||
for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
|
||||
SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
|
||||
|
||||
// The mask element. This indexes into the input.
|
||||
int Idx = Mask[FirstMaskIdx + MaskOffset];
|
||||
unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
|
||||
-1U : cast<ConstantSDNode>(Arg)->getZExtValue();
|
||||
|
||||
// The input vector this mask element indexes into.
|
||||
unsigned Input = (unsigned)Idx / NewElts;
|
||||
unsigned Input = Idx / NewElts;
|
||||
|
||||
if (Input >= array_lengthof(Inputs)) {
|
||||
// The mask element is "undef" or indexes off the end of the input.
|
||||
SVOps.push_back(DAG.getUNDEF(EltVT));
|
||||
Ops.push_back(DAG.getUNDEF(EltVT));
|
||||
continue;
|
||||
}
|
||||
|
||||
@ -846,22 +854,25 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
|
||||
Idx -= Input * NewElts;
|
||||
|
||||
// Extract the vector element by hand.
|
||||
SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
|
||||
Inputs[Input], DAG.getIntPtrConstant(Idx)));
|
||||
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
|
||||
Inputs[Input], DAG.getIntPtrConstant(Idx)));
|
||||
}
|
||||
|
||||
// Construct the Lo/Hi output using a BUILD_VECTOR.
|
||||
Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
|
||||
Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, &Ops[0], Ops.size());
|
||||
} else if (InputUsed[0] == -1U) {
|
||||
// No input vectors were used! The result is undefined.
|
||||
Output = DAG.getUNDEF(NewVT);
|
||||
} else {
|
||||
// At least one input vector was used. Create a new shuffle vector.
|
||||
SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, dl,
|
||||
MVT::getVectorVT(IdxVT, Ops.size()),
|
||||
&Ops[0], Ops.size());
|
||||
SDValue Op0 = Inputs[InputUsed[0]];
|
||||
// If only one input was used, use an undefined vector for the other.
|
||||
SDValue Op1 = InputUsed[1] == -1U ?
|
||||
DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
|
||||
// At least one input vector was used. Create a new shuffle vector.
|
||||
Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
|
||||
Output = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NewVT, Op0, Op1, NewMask);
|
||||
}
|
||||
|
||||
Ops.clear();
|
||||
@ -1462,15 +1473,18 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
|
||||
|
||||
if (NumOperands == 2) {
|
||||
// Replace concat of two operands with a shuffle.
|
||||
SmallVector<int, 16> MaskOps(WidenNumElts);
|
||||
MVT PtrVT = TLI.getPointerTy();
|
||||
SmallVector<SDValue, 16> MaskOps(WidenNumElts);
|
||||
for (unsigned i=0; i < WidenNumElts/2; ++i) {
|
||||
MaskOps[i] = i;
|
||||
MaskOps[i+WidenNumElts/2] = i+WidenNumElts;
|
||||
MaskOps[i] = DAG.getConstant(i, PtrVT);
|
||||
MaskOps[i+WidenNumElts/2] = DAG.getConstant(i+WidenNumElts, PtrVT);
|
||||
}
|
||||
return DAG.getVectorShuffle(WidenVT, dl,
|
||||
GetWidenedVector(N->getOperand(0)),
|
||||
GetWidenedVector(N->getOperand(1)),
|
||||
&MaskOps[0]);
|
||||
SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl,
|
||||
MVT::getVectorVT(PtrVT, WidenNumElts),
|
||||
&MaskOps[0], WidenNumElts);
|
||||
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT,
|
||||
GetWidenedVector(N->getOperand(0)),
|
||||
GetWidenedVector(N->getOperand(1)), Mask);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1748,7 +1762,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
|
||||
|
||||
SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(SDNode *N) {
|
||||
MVT VT = N->getValueType(0);
|
||||
int NumElts = VT.getVectorNumElements();
|
||||
unsigned NumElts = VT.getVectorNumElements();
|
||||
DebugLoc dl = N->getDebugLoc();
|
||||
|
||||
MVT WidenVT = TLI.getTypeToTransformTo(VT);
|
||||
@ -1758,17 +1772,28 @@ SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(SDNode *N) {
|
||||
SDValue InOp2 = GetWidenedVector(N->getOperand(1));
|
||||
|
||||
// Adjust mask based on new input vector length.
|
||||
const int *Mask = cast<ShuffleVectorSDNode>(N)->getMask();
|
||||
SmallVector<int, 16> NewMask;
|
||||
for (int i = 0; i < NumElts; ++i) {
|
||||
if (Mask[i] < NumElts)
|
||||
NewMask.push_back(Mask[i]);
|
||||
else
|
||||
NewMask.push_back(Mask[i] - NumElts + WidenNumElts);
|
||||
SDValue Mask = N->getOperand(2);
|
||||
SmallVector<SDValue, 16> MaskOps(WidenNumElts);
|
||||
MVT IdxVT = Mask.getValueType().getVectorElementType();
|
||||
for (unsigned i = 0; i < NumElts; ++i) {
|
||||
SDValue Arg = Mask.getOperand(i);
|
||||
if (Arg.getOpcode() == ISD::UNDEF)
|
||||
MaskOps[i] = Arg;
|
||||
else {
|
||||
unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
|
||||
if (Idx < NumElts)
|
||||
MaskOps[i] = Arg;
|
||||
else
|
||||
MaskOps[i] = DAG.getConstant(Idx - NumElts + WidenNumElts, IdxVT);
|
||||
}
|
||||
}
|
||||
for (unsigned i = NumElts; i < WidenNumElts; ++i)
|
||||
NewMask.push_back(-1);
|
||||
return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
|
||||
MaskOps[i] = DAG.getUNDEF(IdxVT);
|
||||
SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR, dl,
|
||||
MVT::getVectorVT(IdxVT, WidenNumElts),
|
||||
&MaskOps[0], WidenNumElts);
|
||||
|
||||
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, InOp1, InOp2, NewMask);
|
||||
}
|
||||
|
||||
SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
|
||||
|
@ -456,13 +456,6 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
|
||||
ID.AddInteger(AT->getRawSubclassData());
|
||||
break;
|
||||
}
|
||||
case ISD::VECTOR_SHUFFLE: {
|
||||
const int *Mask = cast<ShuffleVectorSDNode>(N)->getMask();
|
||||
for (unsigned i = 0, e = N->getValueType(0).getVectorNumElements();
|
||||
i != e; ++i)
|
||||
ID.AddInteger(Mask[i]);
|
||||
break;
|
||||
}
|
||||
} // end switch (N->getOpcode())
|
||||
}
|
||||
|
||||
@ -769,6 +762,12 @@ void SelectionDAG::VerifyNode(SDNode *N) {
|
||||
assert(N->getValueType(0).isVector() && "Wrong return type!");
|
||||
assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() &&
|
||||
"Wrong number of operands!");
|
||||
MVT EltVT = N->getValueType(0).getVectorElementType();
|
||||
for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I)
|
||||
assert((I->getValueType() == EltVT ||
|
||||
(EltVT.isInteger() && I->getValueType().isInteger() &&
|
||||
EltVT.bitsLE(I->getValueType()))) &&
|
||||
"Wrong operand type!");
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -1127,110 +1126,6 @@ SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
|
||||
return SDValue(CondCodeNodes[Cond], 0);
|
||||
}
|
||||
|
||||
static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) {
|
||||
std::swap(N1, N2);
|
||||
int NElts = M.size();
|
||||
for (int i = 0; i != NElts; ++i) {
|
||||
if (M[i] >= NElts)
|
||||
M[i] -= NElts;
|
||||
else if (M[i] >= 0)
|
||||
M[i] += NElts;
|
||||
}
|
||||
}
|
||||
|
||||
SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1,
|
||||
SDValue N2, const int *Mask) {
|
||||
assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE");
|
||||
assert(VT.isVector() && N1.getValueType().isVector() &&
|
||||
"Vector Shuffle VTs must be a vectors");
|
||||
assert(VT.getVectorElementType() == N1.getValueType().getVectorElementType()
|
||||
&& "Vector Shuffle VTs must have same element type");
|
||||
|
||||
// Canonicalize shuffle undef, undef -> undef
|
||||
if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF)
|
||||
return N1;
|
||||
|
||||
// Validate that all the indices past in in Mask are within the range of
|
||||
// elements input to the shuffle.
|
||||
int NElts = VT.getVectorNumElements();
|
||||
SmallVector<int, 8> MaskVec;
|
||||
for (int i = 0; i != NElts; ++i) {
|
||||
if (Mask[i] >= (NElts * 2)) {
|
||||
assert(0 && "Index out of range");
|
||||
return SDValue();
|
||||
}
|
||||
MaskVec.push_back(Mask[i]);
|
||||
}
|
||||
|
||||
// Canonicalize shuffle v, v -> v, undef
|
||||
if (N1 == N2) {
|
||||
N2 = getUNDEF(VT);
|
||||
for (int i = 0; i != NElts; ++i)
|
||||
if (MaskVec[i] >= NElts) MaskVec[i] -= NElts;
|
||||
}
|
||||
|
||||
// Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
|
||||
if (N1.getOpcode() == ISD::UNDEF)
|
||||
commuteShuffle(N1, N2, MaskVec);
|
||||
|
||||
// Canonicalize all index into lhs, -> shuffle lhs, undef
|
||||
// Canonicalize all index into rhs, -> shuffle rhs, undef
|
||||
bool AllLHS = true, AllRHS = true;
|
||||
bool N2Undef = N2.getOpcode() == ISD::UNDEF;
|
||||
for (int i = 0; i != NElts; ++i) {
|
||||
if (MaskVec[i] >= NElts) {
|
||||
if (N2Undef)
|
||||
MaskVec[i] = -1;
|
||||
else
|
||||
AllLHS = false;
|
||||
} else if (MaskVec[i] >= 0) {
|
||||
AllRHS = false;
|
||||
}
|
||||
}
|
||||
if (AllLHS && AllRHS)
|
||||
return getUNDEF(VT);
|
||||
if (AllLHS)
|
||||
N2 = getUNDEF(VT);
|
||||
if (AllRHS) {
|
||||
N1 = getUNDEF(VT);
|
||||
commuteShuffle(N1, N2, MaskVec);
|
||||
}
|
||||
|
||||
// If Identity shuffle, or all shuffle in to undef, return that node.
|
||||
bool AllUndef = true;
|
||||
bool Identity = true;
|
||||
for (int i = 0; i < NElts; ++i) {
|
||||
if (MaskVec[i] >= 0 && MaskVec[i] != i) Identity = false;
|
||||
if (MaskVec[i] >= 0) AllUndef = false;
|
||||
}
|
||||
if (Identity)
|
||||
return N1;
|
||||
if (AllUndef)
|
||||
return getUNDEF(VT);
|
||||
|
||||
FoldingSetNodeID ID;
|
||||
SDValue Ops[2] = { N1, N2 };
|
||||
AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2);
|
||||
for (int i = 0; i != NElts; ++i)
|
||||
ID.AddInteger(MaskVec[i]);
|
||||
|
||||
void* IP = 0;
|
||||
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
|
||||
return SDValue(E, 0);
|
||||
|
||||
// Allocate the mask array for the node out of the BumpPtrAllocator, since
|
||||
// SDNode doesn't have access to it. This memory will be "leaked" when
|
||||
// the node is deallocated, but recovered when the NodeAllocator is released.
|
||||
int *MaskAlloc = OperandAllocator.Allocate<int>(NElts);
|
||||
memcpy(MaskAlloc, &MaskVec[0], NElts * sizeof(int));
|
||||
|
||||
ShuffleVectorSDNode *N = NodeAllocator.Allocate<ShuffleVectorSDNode>();
|
||||
new (N) ShuffleVectorSDNode(VT, dl, N1, N2, MaskAlloc);
|
||||
CSEMap.InsertNode(N, IP);
|
||||
AllNodes.push_back(N);
|
||||
return SDValue(N, 0);
|
||||
}
|
||||
|
||||
SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl,
|
||||
SDValue Val, SDValue DTy,
|
||||
SDValue STy, SDValue Rnd, SDValue Sat,
|
||||
@ -2192,18 +2087,19 @@ bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const {
|
||||
SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) {
|
||||
MVT VT = N->getValueType(0);
|
||||
DebugLoc dl = N->getDebugLoc();
|
||||
const int *PermMask = cast<ShuffleVectorSDNode>(N)->getMask();
|
||||
if (PermMask[i] < 0)
|
||||
SDValue PermMask = N->getOperand(2);
|
||||
SDValue Idx = PermMask.getOperand(i);
|
||||
if (Idx.getOpcode() == ISD::UNDEF)
|
||||
return getUNDEF(VT.getVectorElementType());
|
||||
int Index = PermMask[i];
|
||||
int NumElems = VT.getVectorNumElements();
|
||||
unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
|
||||
unsigned NumElems = PermMask.getNumOperands();
|
||||
SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
|
||||
Index %= NumElems;
|
||||
|
||||
if (V.getOpcode() == ISD::BIT_CONVERT) {
|
||||
V = V.getOperand(0);
|
||||
MVT VVT = V.getValueType();
|
||||
if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems)
|
||||
if (!VVT.isVector() || VVT.getVectorNumElements() != NumElems)
|
||||
return SDValue();
|
||||
}
|
||||
if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
|
||||
@ -2897,7 +2793,12 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
|
||||
}
|
||||
break;
|
||||
case ISD::VECTOR_SHUFFLE:
|
||||
assert(0 && "should use getVectorShuffle constructor!");
|
||||
assert(N1.getValueType() == N2.getValueType() &&
|
||||
N1.getValueType().isVector() &&
|
||||
VT.isVector() && N3.getValueType().isVector() &&
|
||||
N3.getOpcode() == ISD::BUILD_VECTOR &&
|
||||
VT.getVectorNumElements() == N3.getNumOperands() &&
|
||||
"Illegal VECTOR_SHUFFLE node!");
|
||||
break;
|
||||
case ISD::BIT_CONVERT:
|
||||
// Fold bit_convert nodes from a type to themselves.
|
||||
@ -5421,14 +5322,14 @@ void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const {
|
||||
|
||||
void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const {
|
||||
if (!isTargetOpcode() && getOpcode() == ISD::VECTOR_SHUFFLE) {
|
||||
const int *Mask = cast<ShuffleVectorSDNode>(this)->getMask();
|
||||
SDNode *Mask = getOperand(2).getNode();
|
||||
OS << "<";
|
||||
for (unsigned i = 0, e = ValueList[0].getVectorNumElements(); i != e; ++i) {
|
||||
for (unsigned i = 0, e = Mask->getNumOperands(); i != e; ++i) {
|
||||
if (i) OS << ",";
|
||||
if (Mask[i] < 0)
|
||||
if (Mask->getOperand(i).getOpcode() == ISD::UNDEF)
|
||||
OS << "u";
|
||||
else
|
||||
OS << Mask[i];
|
||||
OS << cast<ConstantSDNode>(Mask->getOperand(i))->getZExtValue();
|
||||
}
|
||||
OS << ">";
|
||||
}
|
||||
@ -5709,13 +5610,3 @@ bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue,
|
||||
SplatBitSize = sz;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) {
|
||||
int Idx = -1;
|
||||
for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
|
||||
if (Idx < 0) Idx = Mask[i];
|
||||
if (Mask[i] >= 0 && Mask[i] != Idx)
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
@ -870,7 +870,8 @@ SDValue SelectionDAGLowering::getValue(const Value *V) {
|
||||
if (ConstantFP *CFP = dyn_cast<ConstantFP>(C))
|
||||
return N = DAG.getConstantFP(*CFP, VT);
|
||||
|
||||
if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
|
||||
if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) &&
|
||||
!V->getType()->isAggregateType())
|
||||
return N = DAG.getUNDEF(VT);
|
||||
|
||||
if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
|
||||
@ -924,11 +925,14 @@ SDValue SelectionDAGLowering::getValue(const Value *V) {
|
||||
for (unsigned i = 0; i != NumElements; ++i)
|
||||
Ops.push_back(getValue(CP->getOperand(i)));
|
||||
} else {
|
||||
assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
|
||||
assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
|
||||
"Unknown vector constant!");
|
||||
MVT EltVT = TLI.getValueType(VecTy->getElementType());
|
||||
|
||||
SDValue Op;
|
||||
if (EltVT.isFloatingPoint())
|
||||
if (isa<UndefValue>(C))
|
||||
Op = DAG.getUNDEF(EltVT);
|
||||
else if (EltVT.isFloatingPoint())
|
||||
Op = DAG.getConstantFP(0, EltVT);
|
||||
else
|
||||
Op = DAG.getConstant(0, EltVT);
|
||||
@ -2431,42 +2435,37 @@ void SelectionDAGLowering::visitExtractElement(User &I) {
|
||||
|
||||
// Utility for visitShuffleVector - Returns true if the mask is mask starting
|
||||
// from SIndx and increasing to the element length (undefs are allowed).
|
||||
static bool SequentialMask(SmallVectorImpl<int> &Mask, int SIndx) {
|
||||
int MaskNumElts = Mask.size();
|
||||
for (int i = 0; i != MaskNumElts; ++i)
|
||||
if ((Mask[i] >= 0) && (Mask[i] != i + SIndx))
|
||||
return false;
|
||||
static bool SequentialMask(SDValue Mask, unsigned SIndx) {
|
||||
unsigned MaskNumElts = Mask.getNumOperands();
|
||||
for (unsigned i = 0; i != MaskNumElts; ++i) {
|
||||
if (Mask.getOperand(i).getOpcode() != ISD::UNDEF) {
|
||||
unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
|
||||
if (Idx != i + SIndx)
|
||||
return false;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
void SelectionDAGLowering::visitShuffleVector(User &I) {
|
||||
SmallVector<int, 8> Mask;
|
||||
SDValue Src1 = getValue(I.getOperand(0));
|
||||
SDValue Src2 = getValue(I.getOperand(1));
|
||||
SDValue Mask = getValue(I.getOperand(2));
|
||||
|
||||
// Convert the ConstantVector mask operand into an array of ints, with -1
|
||||
// representing undef values.
|
||||
SmallVector<Constant*, 8> MaskElts;
|
||||
cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
|
||||
int MaskNumElts = MaskElts.size();
|
||||
for (int i = 0; i != MaskNumElts; ++i) {
|
||||
if (isa<UndefValue>(MaskElts[i]))
|
||||
Mask.push_back(-1);
|
||||
else
|
||||
Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
|
||||
}
|
||||
|
||||
MVT VT = TLI.getValueType(I.getType());
|
||||
MVT SrcVT = Src1.getValueType();
|
||||
int MaskNumElts = Mask.getNumOperands();
|
||||
int SrcNumElts = SrcVT.getVectorNumElements();
|
||||
|
||||
if (SrcNumElts == MaskNumElts) {
|
||||
setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
|
||||
&Mask[0]));
|
||||
setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
|
||||
VT, Src1, Src2, Mask));
|
||||
return;
|
||||
}
|
||||
|
||||
// Normalize the shuffle vector since mask and vector length don't match.
|
||||
MVT MaskEltVT = Mask.getValueType().getVectorElementType();
|
||||
|
||||
if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
|
||||
// Mask is longer than the source vectors and is a multiple of the source
|
||||
// vectors. We can use concatenate vector to make the mask and vectors
|
||||
@ -2480,33 +2479,44 @@ void SelectionDAGLowering::visitShuffleVector(User &I) {
|
||||
|
||||
// Pad both vectors with undefs to make them the same length as the mask.
|
||||
unsigned NumConcat = MaskNumElts / SrcNumElts;
|
||||
bool Src1U = Src1.getOpcode() == ISD::UNDEF;
|
||||
bool Src2U = Src2.getOpcode() == ISD::UNDEF;
|
||||
SDValue UndefVal = DAG.getUNDEF(SrcVT);
|
||||
|
||||
SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
|
||||
SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
|
||||
SDValue* MOps1 = new SDValue[NumConcat];
|
||||
SDValue* MOps2 = new SDValue[NumConcat];
|
||||
MOps1[0] = Src1;
|
||||
MOps2[0] = Src2;
|
||||
|
||||
Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
|
||||
getCurDebugLoc(), VT,
|
||||
&MOps1[0], NumConcat);
|
||||
Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
|
||||
getCurDebugLoc(), VT,
|
||||
&MOps2[0], NumConcat);
|
||||
for (unsigned i = 1; i != NumConcat; ++i) {
|
||||
MOps1[i] = UndefVal;
|
||||
MOps2[i] = UndefVal;
|
||||
}
|
||||
Src1 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
|
||||
VT, MOps1, NumConcat);
|
||||
Src2 = DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
|
||||
VT, MOps2, NumConcat);
|
||||
|
||||
delete [] MOps1;
|
||||
delete [] MOps2;
|
||||
|
||||
// Readjust mask for new input vector length.
|
||||
SmallVector<int, 8> MappedOps;
|
||||
SmallVector<SDValue, 8> MappedOps;
|
||||
for (int i = 0; i != MaskNumElts; ++i) {
|
||||
int Idx = Mask[i];
|
||||
if (Idx < SrcNumElts)
|
||||
MappedOps.push_back(Idx);
|
||||
else
|
||||
MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
|
||||
if (Mask.getOperand(i).getOpcode() == ISD::UNDEF) {
|
||||
MappedOps.push_back(Mask.getOperand(i));
|
||||
} else {
|
||||
int Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
|
||||
if (Idx < SrcNumElts)
|
||||
MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
|
||||
else
|
||||
MappedOps.push_back(DAG.getConstant(Idx + MaskNumElts - SrcNumElts,
|
||||
MaskEltVT));
|
||||
}
|
||||
}
|
||||
setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
|
||||
&MappedOps[0]));
|
||||
Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
|
||||
Mask.getValueType(),
|
||||
&MappedOps[0], MappedOps.size());
|
||||
|
||||
setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
|
||||
VT, Src1, Src2, Mask));
|
||||
return;
|
||||
}
|
||||
|
||||
@ -2531,19 +2541,20 @@ void SelectionDAGLowering::visitShuffleVector(User &I) {
|
||||
int MaxRange[2] = {-1, -1};
|
||||
|
||||
for (int i = 0; i != MaskNumElts; ++i) {
|
||||
int Idx = Mask[i];
|
||||
int Input = 0;
|
||||
if (Idx < 0)
|
||||
continue;
|
||||
|
||||
if (Idx >= SrcNumElts) {
|
||||
Input = 1;
|
||||
Idx -= SrcNumElts;
|
||||
SDValue Arg = Mask.getOperand(i);
|
||||
if (Arg.getOpcode() != ISD::UNDEF) {
|
||||
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
|
||||
int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
|
||||
int Input = 0;
|
||||
if (Idx >= SrcNumElts) {
|
||||
Input = 1;
|
||||
Idx -= SrcNumElts;
|
||||
}
|
||||
if (Idx > MaxRange[Input])
|
||||
MaxRange[Input] = Idx;
|
||||
if (Idx < MinRange[Input])
|
||||
MinRange[Input] = Idx;
|
||||
}
|
||||
if (Idx > MaxRange[Input])
|
||||
MaxRange[Input] = Idx;
|
||||
if (Idx < MinRange[Input])
|
||||
MinRange[Input] = Idx;
|
||||
}
|
||||
|
||||
// Check if the access is smaller than the vector size and can we find
|
||||
@ -2585,18 +2596,26 @@ void SelectionDAGLowering::visitShuffleVector(User &I) {
|
||||
}
|
||||
}
|
||||
// Calculate new mask.
|
||||
SmallVector<int, 8> MappedOps;
|
||||
SmallVector<SDValue, 8> MappedOps;
|
||||
for (int i = 0; i != MaskNumElts; ++i) {
|
||||
int Idx = Mask[i];
|
||||
if (Idx < 0)
|
||||
MappedOps.push_back(Idx);
|
||||
else if (Idx < SrcNumElts)
|
||||
MappedOps.push_back(Idx - StartIdx[0]);
|
||||
else
|
||||
MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
|
||||
SDValue Arg = Mask.getOperand(i);
|
||||
if (Arg.getOpcode() == ISD::UNDEF) {
|
||||
MappedOps.push_back(Arg);
|
||||
} else {
|
||||
int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
|
||||
if (Idx < SrcNumElts)
|
||||
MappedOps.push_back(DAG.getConstant(Idx - StartIdx[0], MaskEltVT));
|
||||
else {
|
||||
Idx = Idx - SrcNumElts - StartIdx[1] + MaskNumElts;
|
||||
MappedOps.push_back(DAG.getConstant(Idx, MaskEltVT));
|
||||
}
|
||||
}
|
||||
}
|
||||
setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
|
||||
&MappedOps[0]));
|
||||
Mask = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
|
||||
Mask.getValueType(),
|
||||
&MappedOps[0], MappedOps.size());
|
||||
setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(),
|
||||
VT, Src1, Src2, Mask));
|
||||
return;
|
||||
}
|
||||
}
|
||||
@ -2608,10 +2627,12 @@ void SelectionDAGLowering::visitShuffleVector(User &I) {
|
||||
MVT PtrVT = TLI.getPointerTy();
|
||||
SmallVector<SDValue,8> Ops;
|
||||
for (int i = 0; i != MaskNumElts; ++i) {
|
||||
if (Mask[i] < 0) {
|
||||
SDValue Arg = Mask.getOperand(i);
|
||||
if (Arg.getOpcode() == ISD::UNDEF) {
|
||||
Ops.push_back(DAG.getUNDEF(EltVT));
|
||||
} else {
|
||||
int Idx = Mask[i];
|
||||
assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
|
||||
int Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
|
||||
if (Idx < SrcNumElts)
|
||||
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
|
||||
EltVT, Src1, DAG.getConstant(Idx, PtrVT)));
|
||||
|
@ -1672,7 +1672,7 @@ SPU::LowerV2I64Splat(MVT OpVT, SelectionDAG& DAG, uint64_t SplatVal,
|
||||
static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
|
||||
SDValue V1 = Op.getOperand(0);
|
||||
SDValue V2 = Op.getOperand(1);
|
||||
const int *PermMask = cast<ShuffleVectorSDNode>(Op)->getMask();
|
||||
SDValue PermMask = Op.getOperand(2);
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
|
||||
if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
|
||||
@ -1703,40 +1703,39 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
|
||||
} else
|
||||
assert(0 && "Unhandled vector type in LowerVECTOR_SHUFFLE");
|
||||
|
||||
for (unsigned i = 0; i != MaxElts; ++i) {
|
||||
if (PermMask[i] < 0)
|
||||
continue;
|
||||
|
||||
unsigned SrcElt = PermMask[i];
|
||||
for (unsigned i = 0; i != PermMask.getNumOperands(); ++i) {
|
||||
if (PermMask.getOperand(i).getOpcode() != ISD::UNDEF) {
|
||||
unsigned SrcElt = cast<ConstantSDNode > (PermMask.getOperand(i))->getZExtValue();
|
||||
|
||||
if (monotonic) {
|
||||
if (SrcElt >= V2EltIdx0) {
|
||||
if (1 >= (++EltsFromV2)) {
|
||||
V2Elt = (V2EltIdx0 - SrcElt) << 2;
|
||||
if (monotonic) {
|
||||
if (SrcElt >= V2EltIdx0) {
|
||||
if (1 >= (++EltsFromV2)) {
|
||||
V2Elt = (V2EltIdx0 - SrcElt) << 2;
|
||||
}
|
||||
} else if (CurrElt != SrcElt) {
|
||||
monotonic = false;
|
||||
}
|
||||
} else if (CurrElt != SrcElt) {
|
||||
monotonic = false;
|
||||
|
||||
++CurrElt;
|
||||
}
|
||||
|
||||
++CurrElt;
|
||||
}
|
||||
|
||||
if (rotate) {
|
||||
if (PrevElt > 0 && SrcElt < MaxElts) {
|
||||
if ((PrevElt == SrcElt - 1)
|
||||
|| (PrevElt == MaxElts - 1 && SrcElt == 0)) {
|
||||
if (rotate) {
|
||||
if (PrevElt > 0 && SrcElt < MaxElts) {
|
||||
if ((PrevElt == SrcElt - 1)
|
||||
|| (PrevElt == MaxElts - 1 && SrcElt == 0)) {
|
||||
PrevElt = SrcElt;
|
||||
if (SrcElt == 0)
|
||||
V0Elt = i;
|
||||
} else {
|
||||
rotate = false;
|
||||
}
|
||||
} else if (PrevElt == 0) {
|
||||
// First time through, need to keep track of previous element
|
||||
PrevElt = SrcElt;
|
||||
if (SrcElt == 0)
|
||||
V0Elt = i;
|
||||
} else {
|
||||
// This isn't a rotation, takes elements from vector 2
|
||||
rotate = false;
|
||||
}
|
||||
} else if (PrevElt == 0) {
|
||||
// First time through, need to keep track of previous element
|
||||
PrevElt = SrcElt;
|
||||
} else {
|
||||
// This isn't a rotation, takes elements from vector 2
|
||||
rotate = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1769,8 +1768,12 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
|
||||
unsigned BytesPerElement = EltVT.getSizeInBits()/8;
|
||||
|
||||
SmallVector<SDValue, 16> ResultMask;
|
||||
for (unsigned i = 0, e = MaxElts; i != e; ++i) {
|
||||
unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
|
||||
for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
|
||||
unsigned SrcElt;
|
||||
if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
|
||||
SrcElt = 0;
|
||||
else
|
||||
SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getZExtValue();
|
||||
|
||||
for (unsigned j = 0; j < BytesPerElement; ++j) {
|
||||
ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
|
||||
|
@ -456,22 +456,22 @@ static bool isFloatingPointZero(SDValue Op) {
|
||||
|
||||
/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
|
||||
/// true if Op is undef or if it matches the specified value.
|
||||
static bool isConstantOrUndef(int Op, int Val) {
|
||||
return Op < 0 || Op == Val;
|
||||
static bool isConstantOrUndef(SDValue Op, unsigned Val) {
|
||||
return Op.getOpcode() == ISD::UNDEF ||
|
||||
cast<ConstantSDNode>(Op)->getZExtValue() == Val;
|
||||
}
|
||||
|
||||
/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
|
||||
/// VPKUHUM instruction.
|
||||
bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
|
||||
const int *Mask = N->getMask();
|
||||
bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
|
||||
if (!isUnary) {
|
||||
for (unsigned i = 0; i != 16; ++i)
|
||||
if (!isConstantOrUndef(Mask[i], i*2+1))
|
||||
if (!isConstantOrUndef(N->getOperand(i), i*2+1))
|
||||
return false;
|
||||
} else {
|
||||
for (unsigned i = 0; i != 8; ++i)
|
||||
if (!isConstantOrUndef(Mask[i], i*2+1) ||
|
||||
!isConstantOrUndef(Mask[i+8], i*2+1))
|
||||
if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
|
||||
!isConstantOrUndef(N->getOperand(i+8), i*2+1))
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
@ -479,19 +479,18 @@ bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
|
||||
|
||||
/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
|
||||
/// VPKUWUM instruction.
|
||||
bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
|
||||
const int *Mask = N->getMask();
|
||||
bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
|
||||
if (!isUnary) {
|
||||
for (unsigned i = 0; i != 16; i += 2)
|
||||
if (!isConstantOrUndef(Mask[i ], i*2+2) ||
|
||||
!isConstantOrUndef(Mask[i+1], i*2+3))
|
||||
if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
|
||||
!isConstantOrUndef(N->getOperand(i+1), i*2+3))
|
||||
return false;
|
||||
} else {
|
||||
for (unsigned i = 0; i != 8; i += 2)
|
||||
if (!isConstantOrUndef(Mask[i ], i*2+2) ||
|
||||
!isConstantOrUndef(Mask[i+1], i*2+3) ||
|
||||
!isConstantOrUndef(Mask[i+8], i*2+2) ||
|
||||
!isConstantOrUndef(Mask[i+9], i*2+3))
|
||||
if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
|
||||
!isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
|
||||
!isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
|
||||
!isConstantOrUndef(N->getOperand(i+9), i*2+3))
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
@ -499,29 +498,27 @@ bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
|
||||
|
||||
/// isVMerge - Common function, used to match vmrg* shuffles.
|
||||
///
|
||||
static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
|
||||
static bool isVMerge(SDNode *N, unsigned UnitSize,
|
||||
unsigned LHSStart, unsigned RHSStart) {
|
||||
assert(N->getValueType(0) == MVT::v16i8 &&
|
||||
"PPC only supports shuffles by bytes!");
|
||||
assert(N->getOpcode() == ISD::BUILD_VECTOR &&
|
||||
N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
|
||||
assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
|
||||
"Unsupported merge size!");
|
||||
|
||||
const int *Mask = N->getMask();
|
||||
for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
|
||||
for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
|
||||
if (!isConstantOrUndef(Mask[i*UnitSize*2+j],
|
||||
if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
|
||||
LHSStart+j+i*UnitSize) ||
|
||||
!isConstantOrUndef(Mask[i*UnitSize*2+UnitSize+j],
|
||||
!isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
|
||||
RHSStart+j+i*UnitSize))
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
return true;
|
||||
}
|
||||
|
||||
/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
|
||||
/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
|
||||
bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
|
||||
bool isUnary) {
|
||||
bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
|
||||
if (!isUnary)
|
||||
return isVMerge(N, UnitSize, 8, 24);
|
||||
return isVMerge(N, UnitSize, 8, 8);
|
||||
@ -529,8 +526,7 @@ bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
|
||||
|
||||
/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
|
||||
/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
|
||||
bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
|
||||
bool isUnary) {
|
||||
bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
|
||||
if (!isUnary)
|
||||
return isVMerge(N, UnitSize, 0, 16);
|
||||
return isVMerge(N, UnitSize, 0, 0);
|
||||
@ -540,92 +536,91 @@ bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
|
||||
/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
|
||||
/// amount, otherwise return -1.
|
||||
int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
|
||||
assert(N->getValueType(0) == MVT::v16i8 &&
|
||||
"PPC only supports shuffles by bytes!");
|
||||
|
||||
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
|
||||
|
||||
assert(N->getOpcode() == ISD::BUILD_VECTOR &&
|
||||
N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
|
||||
// Find the first non-undef value in the shuffle mask.
|
||||
const int *Mask = SVOp->getMask();
|
||||
unsigned i;
|
||||
for (i = 0; i != 16 && Mask[i] < 0; ++i)
|
||||
for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
|
||||
/*search*/;
|
||||
|
||||
if (i == 16) return -1; // all undef.
|
||||
|
||||
// Otherwise, check to see if the rest of the elements are consecutively
|
||||
// Otherwise, check to see if the rest of the elements are consequtively
|
||||
// numbered from this value.
|
||||
unsigned ShiftAmt = Mask[i];
|
||||
unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getZExtValue();
|
||||
if (ShiftAmt < i) return -1;
|
||||
ShiftAmt -= i;
|
||||
|
||||
if (!isUnary) {
|
||||
// Check the rest of the elements to see if they are consecutive.
|
||||
// Check the rest of the elements to see if they are consequtive.
|
||||
for (++i; i != 16; ++i)
|
||||
if (!isConstantOrUndef(Mask[i], ShiftAmt+i))
|
||||
if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
|
||||
return -1;
|
||||
} else {
|
||||
// Check the rest of the elements to see if they are consecutive.
|
||||
// Check the rest of the elements to see if they are consequtive.
|
||||
for (++i; i != 16; ++i)
|
||||
if (!isConstantOrUndef(Mask[i], (ShiftAmt+i) & 15))
|
||||
if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
|
||||
return -1;
|
||||
}
|
||||
|
||||
return ShiftAmt;
|
||||
}
|
||||
|
||||
/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a splat of a single element that is suitable for input to
|
||||
/// VSPLTB/VSPLTH/VSPLTW.
|
||||
bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
|
||||
assert(N->getValueType(0) == MVT::v16i8 &&
|
||||
bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
|
||||
assert(N->getOpcode() == ISD::BUILD_VECTOR &&
|
||||
N->getNumOperands() == 16 &&
|
||||
(EltSize == 1 || EltSize == 2 || EltSize == 4));
|
||||
|
||||
// This is a splat operation if each element of the permute is the same, and
|
||||
// if the value doesn't reference the second vector.
|
||||
const int *Mask = N->getMask();
|
||||
unsigned ElementBase = Mask[0];
|
||||
|
||||
// FIXME: Handle UNDEF elements too!
|
||||
if (ElementBase >= 16)
|
||||
unsigned ElementBase = 0;
|
||||
SDValue Elt = N->getOperand(0);
|
||||
if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
|
||||
ElementBase = EltV->getZExtValue();
|
||||
else
|
||||
return false; // FIXME: Handle UNDEF elements too!
|
||||
|
||||
if (cast<ConstantSDNode>(Elt)->getZExtValue() >= 16)
|
||||
return false;
|
||||
|
||||
// Check that the indices are consecutive, in the case of a multi-byte element
|
||||
// splatted with a v16i8 mask.
|
||||
for (unsigned i = 1; i != EltSize; ++i)
|
||||
if (Mask[i] < 0 || Mask[i] != (int)(i+ElementBase))
|
||||
// Check that they are consequtive.
|
||||
for (unsigned i = 1; i != EltSize; ++i) {
|
||||
if (!isa<ConstantSDNode>(N->getOperand(i)) ||
|
||||
cast<ConstantSDNode>(N->getOperand(i))->getZExtValue() != i+ElementBase)
|
||||
return false;
|
||||
}
|
||||
|
||||
assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
|
||||
for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
|
||||
if (Mask[i] < 0) continue;
|
||||
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
|
||||
assert(isa<ConstantSDNode>(N->getOperand(i)) &&
|
||||
"Invalid VECTOR_SHUFFLE mask!");
|
||||
for (unsigned j = 0; j != EltSize; ++j)
|
||||
if (Mask[i+j] != Mask[j])
|
||||
if (N->getOperand(i+j) != N->getOperand(j))
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/// isAllNegativeZeroVector - Returns true if all elements of build_vector
|
||||
/// are -0.0.
|
||||
bool PPC::isAllNegativeZeroVector(SDNode *N) {
|
||||
BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
|
||||
|
||||
APInt APVal, APUndef;
|
||||
unsigned BitSize;
|
||||
bool HasAnyUndefs;
|
||||
|
||||
if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32))
|
||||
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
|
||||
assert(N->getOpcode() == ISD::BUILD_VECTOR);
|
||||
if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
|
||||
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
|
||||
return CFP->getValueAPF().isNegZero();
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
|
||||
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
|
||||
unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
|
||||
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
|
||||
assert(isSplatShuffleMask(SVOp, EltSize));
|
||||
return SVOp->getMask()[0] / EltSize;
|
||||
assert(isSplatShuffleMask(N, EltSize));
|
||||
return cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() / EltSize;
|
||||
}
|
||||
|
||||
/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
|
||||
@ -3154,10 +3149,11 @@ static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
|
||||
LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
|
||||
RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
|
||||
|
||||
int Ops[16];
|
||||
SDValue Ops[16];
|
||||
for (unsigned i = 0; i != 16; ++i)
|
||||
Ops[i] = i + Amt;
|
||||
SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
|
||||
Ops[i] = DAG.getConstant(i+Amt, MVT::i8);
|
||||
SDValue T = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v16i8, LHS, RHS,
|
||||
DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops,16));
|
||||
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
|
||||
}
|
||||
|
||||
@ -3358,7 +3354,7 @@ static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
|
||||
OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
|
||||
OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
|
||||
|
||||
int ShufIdxs[16];
|
||||
unsigned ShufIdxs[16];
|
||||
switch (OpNum) {
|
||||
default: assert(0 && "Unknown i32 permute!");
|
||||
case OP_VMRGHW:
|
||||
@ -3396,11 +3392,13 @@ static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
|
||||
case OP_VSLDOI12:
|
||||
return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
|
||||
}
|
||||
MVT VT = OpLHS.getValueType();
|
||||
OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS);
|
||||
OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS);
|
||||
SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
|
||||
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
|
||||
SDValue Ops[16];
|
||||
for (unsigned i = 0; i != 16; ++i)
|
||||
Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8);
|
||||
|
||||
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, OpLHS.getValueType(),
|
||||
OpLHS, OpRHS,
|
||||
DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops, 16));
|
||||
}
|
||||
|
||||
/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
|
||||
@ -3408,30 +3406,28 @@ static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
|
||||
/// return the code it can be lowered into. Worst case, it can always be
|
||||
/// lowered into a vperm.
|
||||
SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
|
||||
SelectionDAG &DAG) {
|
||||
SelectionDAG &DAG) {
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
SDValue V1 = Op.getOperand(0);
|
||||
SDValue V2 = Op.getOperand(1);
|
||||
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
|
||||
const int *PermMask = SVOp->getMask();
|
||||
MVT VT = Op.getValueType();
|
||||
SDValue PermMask = Op.getOperand(2);
|
||||
|
||||
// Cases that are handled by instructions that take permute immediates
|
||||
// (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
|
||||
// selected by the instruction selector.
|
||||
if (V2.getOpcode() == ISD::UNDEF) {
|
||||
if (PPC::isSplatShuffleMask(SVOp, 1) ||
|
||||
PPC::isSplatShuffleMask(SVOp, 2) ||
|
||||
PPC::isSplatShuffleMask(SVOp, 4) ||
|
||||
PPC::isVPKUWUMShuffleMask(SVOp, true) ||
|
||||
PPC::isVPKUHUMShuffleMask(SVOp, true) ||
|
||||
PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
|
||||
PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
|
||||
PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
|
||||
PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
|
||||
PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
|
||||
PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
|
||||
PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
|
||||
if (PPC::isSplatShuffleMask(PermMask.getNode(), 1) ||
|
||||
PPC::isSplatShuffleMask(PermMask.getNode(), 2) ||
|
||||
PPC::isSplatShuffleMask(PermMask.getNode(), 4) ||
|
||||
PPC::isVPKUWUMShuffleMask(PermMask.getNode(), true) ||
|
||||
PPC::isVPKUHUMShuffleMask(PermMask.getNode(), true) ||
|
||||
PPC::isVSLDOIShuffleMask(PermMask.getNode(), true) != -1 ||
|
||||
PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, true) ||
|
||||
PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, true) ||
|
||||
PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, true) ||
|
||||
PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, true) ||
|
||||
PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, true) ||
|
||||
PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, true)) {
|
||||
return Op;
|
||||
}
|
||||
}
|
||||
@ -3439,15 +3435,15 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
|
||||
// Altivec has a variety of "shuffle immediates" that take two vector inputs
|
||||
// and produce a fixed permutation. If any of these match, do not lower to
|
||||
// VPERM.
|
||||
if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
|
||||
PPC::isVPKUHUMShuffleMask(SVOp, false) ||
|
||||
PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
|
||||
PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
|
||||
PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
|
||||
PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
|
||||
PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
|
||||
PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
|
||||
PPC::isVMRGHShuffleMask(SVOp, 4, false))
|
||||
if (PPC::isVPKUWUMShuffleMask(PermMask.getNode(), false) ||
|
||||
PPC::isVPKUHUMShuffleMask(PermMask.getNode(), false) ||
|
||||
PPC::isVSLDOIShuffleMask(PermMask.getNode(), false) != -1 ||
|
||||
PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, false) ||
|
||||
PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, false) ||
|
||||
PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, false) ||
|
||||
PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, false) ||
|
||||
PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, false) ||
|
||||
PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, false))
|
||||
return Op;
|
||||
|
||||
// Check to see if this is a shuffle of 4-byte values. If so, we can use our
|
||||
@ -3457,10 +3453,11 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
|
||||
for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
|
||||
unsigned EltNo = 8; // Start out undef.
|
||||
for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
|
||||
if (PermMask[i*4+j] < 0)
|
||||
if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
|
||||
continue; // Undef, ignore it.
|
||||
|
||||
unsigned ByteSource = PermMask[i*4+j];
|
||||
unsigned ByteSource =
|
||||
cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getZExtValue();
|
||||
if ((ByteSource & 3) != j) {
|
||||
isFourElementShuffle = false;
|
||||
break;
|
||||
@ -3512,8 +3509,12 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
|
||||
unsigned BytesPerElement = EltVT.getSizeInBits()/8;
|
||||
|
||||
SmallVector<SDValue, 16> ResultMask;
|
||||
for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
|
||||
unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
|
||||
for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
|
||||
unsigned SrcElt;
|
||||
if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
|
||||
SrcElt = 0;
|
||||
else
|
||||
SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getZExtValue();
|
||||
|
||||
for (unsigned j = 0; j != BytesPerElement; ++j)
|
||||
ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
|
||||
@ -3703,12 +3704,13 @@ SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
|
||||
OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
|
||||
|
||||
// Merge the results together.
|
||||
int Ops[16];
|
||||
SDValue Ops[16];
|
||||
for (unsigned i = 0; i != 8; ++i) {
|
||||
Ops[i*2 ] = 2*i+1;
|
||||
Ops[i*2+1] = 2*i+1+16;
|
||||
Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
|
||||
Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
|
||||
}
|
||||
return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
|
||||
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v16i8, EvenParts, OddParts,
|
||||
DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, Ops, 16));
|
||||
} else {
|
||||
assert(0 && "Unknown mul to lower!");
|
||||
abort();
|
||||
|
@ -175,21 +175,19 @@ namespace llvm {
|
||||
namespace PPC {
|
||||
/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
|
||||
/// VPKUHUM instruction.
|
||||
bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
|
||||
bool isVPKUHUMShuffleMask(SDNode *N, bool isUnary);
|
||||
|
||||
/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
|
||||
/// VPKUWUM instruction.
|
||||
bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
|
||||
bool isVPKUWUMShuffleMask(SDNode *N, bool isUnary);
|
||||
|
||||
/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
|
||||
/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
|
||||
bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
|
||||
bool isUnary);
|
||||
bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
|
||||
|
||||
/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
|
||||
/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
|
||||
bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
|
||||
bool isUnary);
|
||||
bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
|
||||
|
||||
/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
|
||||
/// amount, otherwise return -1.
|
||||
@ -198,7 +196,7 @@ namespace llvm {
|
||||
/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a splat of a single element that is suitable for input to
|
||||
/// VSPLTB/VSPLTH/VSPLTW.
|
||||
bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
|
||||
bool isSplatShuffleMask(SDNode *N, unsigned EltSize);
|
||||
|
||||
/// isAllNegativeZeroVector - Returns true if all elements of build_vector
|
||||
/// are -0.0.
|
||||
|
@ -15,118 +15,96 @@
|
||||
// Altivec transformation functions and pattern fragments.
|
||||
//
|
||||
|
||||
/// VPKUHUM_shuffle_mask/VPKUWUM_shuffle_mask - Return true if this is a valid
|
||||
/// shuffle mask for the VPKUHUM or VPKUWUM instructions.
|
||||
def VPKUHUM_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVPKUHUMShuffleMask(N, false);
|
||||
}]>;
|
||||
def VPKUWUM_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVPKUWUMShuffleMask(N, false);
|
||||
}]>;
|
||||
|
||||
def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
|
||||
def VPKUHUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVPKUHUMShuffleMask(N, true);
|
||||
}]>;
|
||||
def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false);
|
||||
}]>;
|
||||
def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
|
||||
}]>;
|
||||
def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true);
|
||||
def VPKUWUM_unary_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVPKUWUMShuffleMask(N, true);
|
||||
}]>;
|
||||
|
||||
|
||||
def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
|
||||
def VMRGLB_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVMRGLShuffleMask(N, 1, false);
|
||||
}]>;
|
||||
def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
|
||||
def VMRGLH_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVMRGLShuffleMask(N, 2, false);
|
||||
}]>;
|
||||
def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
|
||||
def VMRGLW_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVMRGLShuffleMask(N, 4, false);
|
||||
}]>;
|
||||
def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false);
|
||||
def VMRGHB_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVMRGHShuffleMask(N, 1, false);
|
||||
}]>;
|
||||
def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false);
|
||||
def VMRGHH_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVMRGHShuffleMask(N, 2, false);
|
||||
}]>;
|
||||
def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false);
|
||||
def VMRGHW_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVMRGHShuffleMask(N, 4, false);
|
||||
}]>;
|
||||
|
||||
|
||||
def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
|
||||
def VMRGLB_unary_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVMRGLShuffleMask(N, 1, true);
|
||||
}]>;
|
||||
def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
|
||||
def VMRGLH_unary_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVMRGLShuffleMask(N, 2, true);
|
||||
}]>;
|
||||
def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
|
||||
def VMRGLW_unary_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVMRGLShuffleMask(N, 4, true);
|
||||
}]>;
|
||||
def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true);
|
||||
def VMRGHB_unary_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVMRGHShuffleMask(N, 1, true);
|
||||
}]>;
|
||||
def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true);
|
||||
def VMRGHH_unary_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVMRGHShuffleMask(N, 2, true);
|
||||
}]>;
|
||||
def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true);
|
||||
def VMRGHW_unary_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVMRGHShuffleMask(N, 4, true);
|
||||
}]>;
|
||||
|
||||
|
||||
def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{
|
||||
def VSLDOI_get_imm : SDNodeXForm<build_vector, [{
|
||||
return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
|
||||
}]>;
|
||||
def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
def VSLDOI_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVSLDOIShuffleMask(N, false) != -1;
|
||||
}], VSLDOI_get_imm>;
|
||||
|
||||
|
||||
/// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into
|
||||
/// vector_shuffle(X,undef,mask) by the dag combiner.
|
||||
def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{
|
||||
def VSLDOI_unary_get_imm : SDNodeXForm<build_vector, [{
|
||||
return getI32Imm(PPC::isVSLDOIShuffleMask(N, true));
|
||||
}]>;
|
||||
def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
def VSLDOI_unary_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isVSLDOIShuffleMask(N, true) != -1;
|
||||
}], VSLDOI_unary_get_imm>;
|
||||
|
||||
|
||||
// VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm.
|
||||
def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{
|
||||
def VSPLTB_get_imm : SDNodeXForm<build_vector, [{
|
||||
return getI32Imm(PPC::getVSPLTImmediate(N, 1));
|
||||
}]>;
|
||||
def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1);
|
||||
def VSPLTB_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isSplatShuffleMask(N, 1);
|
||||
}], VSPLTB_get_imm>;
|
||||
def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{
|
||||
def VSPLTH_get_imm : SDNodeXForm<build_vector, [{
|
||||
return getI32Imm(PPC::getVSPLTImmediate(N, 2));
|
||||
}]>;
|
||||
def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2);
|
||||
def VSPLTH_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isSplatShuffleMask(N, 2);
|
||||
}], VSPLTH_get_imm>;
|
||||
def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{
|
||||
def VSPLTW_get_imm : SDNodeXForm<build_vector, [{
|
||||
return getI32Imm(PPC::getVSPLTImmediate(N, 4));
|
||||
}]>;
|
||||
def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4);
|
||||
def VSPLTW_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return PPC::isSplatShuffleMask(N, 4);
|
||||
}], VSPLTW_get_imm>;
|
||||
|
||||
|
||||
@ -290,7 +268,8 @@ def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>;
|
||||
def VSLDOI : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH),
|
||||
"vsldoi $vD, $vA, $vB, $SH", VecFP,
|
||||
[(set VRRC:$vD,
|
||||
(vsldoi_shuffle:$SH (v16i8 VRRC:$vA), VRRC:$vB))]>;
|
||||
(vector_shuffle (v16i8 VRRC:$vA), VRRC:$vB,
|
||||
VSLDOI_shuffle_mask:$SH))]>;
|
||||
|
||||
// VX-Form instructions. AltiVec arithmetic ops.
|
||||
def VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
@ -366,22 +345,28 @@ def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>;
|
||||
|
||||
def VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
"vmrghb $vD, $vA, $vB", VecFP,
|
||||
[(set VRRC:$vD, (vmrghb_shuffle VRRC:$vA, VRRC:$vB))]>;
|
||||
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
||||
VRRC:$vB, VMRGHB_shuffle_mask))]>;
|
||||
def VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
"vmrghh $vD, $vA, $vB", VecFP,
|
||||
[(set VRRC:$vD, (vmrghh_shuffle VRRC:$vA, VRRC:$vB))]>;
|
||||
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
||||
VRRC:$vB, VMRGHH_shuffle_mask))]>;
|
||||
def VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
"vmrghw $vD, $vA, $vB", VecFP,
|
||||
[(set VRRC:$vD, (vmrghw_shuffle VRRC:$vA, VRRC:$vB))]>;
|
||||
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
||||
VRRC:$vB, VMRGHW_shuffle_mask))]>;
|
||||
def VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
"vmrglb $vD, $vA, $vB", VecFP,
|
||||
[(set VRRC:$vD, (vmrglb_shuffle VRRC:$vA, VRRC:$vB))]>;
|
||||
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
||||
VRRC:$vB, VMRGLB_shuffle_mask))]>;
|
||||
def VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
"vmrglh $vD, $vA, $vB", VecFP,
|
||||
[(set VRRC:$vD, (vmrglh_shuffle VRRC:$vA, VRRC:$vB))]>;
|
||||
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
||||
VRRC:$vB, VMRGLH_shuffle_mask))]>;
|
||||
def VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
"vmrglw $vD, $vA, $vB", VecFP,
|
||||
[(set VRRC:$vD, (vmrglw_shuffle VRRC:$vA, VRRC:$vB))]>;
|
||||
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
||||
VRRC:$vB, VMRGLW_shuffle_mask))]>;
|
||||
|
||||
def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
|
||||
def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
|
||||
@ -455,16 +440,16 @@ def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>;
|
||||
|
||||
def VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
|
||||
"vspltb $vD, $vB, $UIMM", VecPerm,
|
||||
[(set VRRC:$vD,
|
||||
(vspltb_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>;
|
||||
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
|
||||
VSPLTB_shuffle_mask:$UIMM))]>;
|
||||
def VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
|
||||
"vsplth $vD, $vB, $UIMM", VecPerm,
|
||||
[(set VRRC:$vD,
|
||||
(vsplth_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>;
|
||||
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
|
||||
VSPLTH_shuffle_mask:$UIMM))]>;
|
||||
def VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
|
||||
"vspltw $vD, $vB, $UIMM", VecPerm,
|
||||
[(set VRRC:$vD,
|
||||
(vspltw_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>;
|
||||
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vB), (undef),
|
||||
VSPLTW_shuffle_mask:$UIMM))]>;
|
||||
|
||||
def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>;
|
||||
def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
|
||||
@ -494,13 +479,13 @@ def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>;
|
||||
def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
|
||||
def VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
"vpkuhum $vD, $vA, $vB", VecFP,
|
||||
[(set VRRC:$vD,
|
||||
(vpkuhum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>;
|
||||
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
||||
VRRC:$vB, VPKUHUM_shuffle_mask))]>;
|
||||
def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
|
||||
def VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
"vpkuwum $vD, $vA, $vB", VecFP,
|
||||
[(set VRRC:$vD,
|
||||
(vpkuwum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>;
|
||||
[(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
|
||||
VRRC:$vB, VPKUWUM_shuffle_mask))]>;
|
||||
def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
|
||||
|
||||
// Vector Unpack.
|
||||
@ -618,25 +603,25 @@ def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>;
|
||||
// Shuffles.
|
||||
|
||||
// Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x)
|
||||
def:Pat<(vsldoi_unary_shuffle:$in (v16i8 VRRC:$vA), undef),
|
||||
(VSLDOI VRRC:$vA, VRRC:$vA, (VSLDOI_unary_get_imm VRRC:$in))>;
|
||||
def:Pat<(vpkuwum_unary_shuffle (v16i8 VRRC:$vA), undef),
|
||||
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VSLDOI_unary_shuffle_mask:$in),
|
||||
(VSLDOI VRRC:$vA, VRRC:$vA, VSLDOI_unary_shuffle_mask:$in)>;
|
||||
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUWUM_unary_shuffle_mask:$in),
|
||||
(VPKUWUM VRRC:$vA, VRRC:$vA)>;
|
||||
def:Pat<(vpkuhum_unary_shuffle (v16i8 VRRC:$vA), undef),
|
||||
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef,VPKUHUM_unary_shuffle_mask:$in),
|
||||
(VPKUHUM VRRC:$vA, VRRC:$vA)>;
|
||||
|
||||
// Match vmrg*(x,x)
|
||||
def:Pat<(vmrglb_unary_shuffle (v16i8 VRRC:$vA), undef),
|
||||
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLB_unary_shuffle_mask:$in),
|
||||
(VMRGLB VRRC:$vA, VRRC:$vA)>;
|
||||
def:Pat<(vmrglh_unary_shuffle (v16i8 VRRC:$vA), undef),
|
||||
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLH_unary_shuffle_mask:$in),
|
||||
(VMRGLH VRRC:$vA, VRRC:$vA)>;
|
||||
def:Pat<(vmrglw_unary_shuffle (v16i8 VRRC:$vA), undef),
|
||||
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGLW_unary_shuffle_mask:$in),
|
||||
(VMRGLW VRRC:$vA, VRRC:$vA)>;
|
||||
def:Pat<(vmrghb_unary_shuffle (v16i8 VRRC:$vA), undef),
|
||||
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHB_unary_shuffle_mask:$in),
|
||||
(VMRGHB VRRC:$vA, VRRC:$vA)>;
|
||||
def:Pat<(vmrghh_unary_shuffle (v16i8 VRRC:$vA), undef),
|
||||
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHH_unary_shuffle_mask:$in),
|
||||
(VMRGHH VRRC:$vA, VRRC:$vA)>;
|
||||
def:Pat<(vmrghw_unary_shuffle (v16i8 VRRC:$vA), undef),
|
||||
def:Pat<(vector_shuffle (v16i8 VRRC:$vA), undef, VMRGHW_unary_shuffle_mask:$in),
|
||||
(VMRGHW VRRC:$vA, VRRC:$vA)>;
|
||||
|
||||
// Logical Operations
|
||||
|
File diff suppressed because it is too large
Load Diff
@ -230,8 +230,7 @@ namespace llvm {
|
||||
|
||||
// VSHL, VSRL - Vector logical left / right shift.
|
||||
VSHL, VSRL,
|
||||
|
||||
// CMPPD, CMPPS - Vector double/float comparison.
|
||||
|
||||
// CMPPD, CMPPS - Vector double/float comparison.
|
||||
CMPPD, CMPPS,
|
||||
|
||||
@ -252,72 +251,80 @@ namespace llvm {
|
||||
namespace X86 {
|
||||
/// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a shuffle of elements that is suitable for input to PSHUFD.
|
||||
bool isPSHUFDMask(ShuffleVectorSDNode *N);
|
||||
bool isPSHUFDMask(SDNode *N);
|
||||
|
||||
/// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a shuffle of elements that is suitable for input to PSHUFD.
|
||||
bool isPSHUFHWMask(ShuffleVectorSDNode *N);
|
||||
bool isPSHUFHWMask(SDNode *N);
|
||||
|
||||
/// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a shuffle of elements that is suitable for input to PSHUFD.
|
||||
bool isPSHUFLWMask(ShuffleVectorSDNode *N);
|
||||
bool isPSHUFLWMask(SDNode *N);
|
||||
|
||||
/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a shuffle of elements that is suitable for input to SHUFP*.
|
||||
bool isSHUFPMask(ShuffleVectorSDNode *N);
|
||||
bool isSHUFPMask(SDNode *N);
|
||||
|
||||
/// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a shuffle of elements that is suitable for input to MOVHLPS.
|
||||
bool isMOVHLPSMask(ShuffleVectorSDNode *N);
|
||||
bool isMOVHLPSMask(SDNode *N);
|
||||
|
||||
/// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
|
||||
/// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
|
||||
/// <2, 3, 2, 3>
|
||||
bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
|
||||
bool isMOVHLPS_v_undef_Mask(SDNode *N);
|
||||
|
||||
/// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
|
||||
bool isMOVLPMask(ShuffleVectorSDNode *N);
|
||||
/// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
|
||||
bool isMOVLPMask(SDNode *N);
|
||||
|
||||
/// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
|
||||
/// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
|
||||
/// as well as MOVLHPS.
|
||||
bool isMOVHPMask(ShuffleVectorSDNode *N);
|
||||
bool isMOVHPMask(SDNode *N);
|
||||
|
||||
/// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a shuffle of elements that is suitable for input to UNPCKL.
|
||||
bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
|
||||
bool isUNPCKLMask(SDNode *N, bool V2IsSplat = false);
|
||||
|
||||
/// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a shuffle of elements that is suitable for input to UNPCKH.
|
||||
bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
|
||||
bool isUNPCKHMask(SDNode *N, bool V2IsSplat = false);
|
||||
|
||||
/// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
|
||||
/// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
|
||||
/// <0, 0, 1, 1>
|
||||
bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
|
||||
bool isUNPCKL_v_undef_Mask(SDNode *N);
|
||||
|
||||
/// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
|
||||
/// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
|
||||
/// <2, 2, 3, 3>
|
||||
bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
|
||||
bool isUNPCKH_v_undef_Mask(SDNode *N);
|
||||
|
||||
/// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a shuffle of elements that is suitable for input to MOVSS,
|
||||
/// MOVSD, and MOVD, i.e. setting the lowest element.
|
||||
bool isMOVLMask(ShuffleVectorSDNode *N);
|
||||
bool isMOVLMask(SDNode *N);
|
||||
|
||||
/// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
|
||||
bool isMOVSHDUPMask(ShuffleVectorSDNode *N);
|
||||
bool isMOVSHDUPMask(SDNode *N);
|
||||
|
||||
/// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
|
||||
bool isMOVSLDUPMask(ShuffleVectorSDNode *N);
|
||||
bool isMOVSLDUPMask(SDNode *N);
|
||||
|
||||
/// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a splat of a single element.
|
||||
bool isSplatMask(SDNode *N);
|
||||
|
||||
/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a splat of zero element.
|
||||
bool isSplatLoMask(SDNode *N);
|
||||
|
||||
/// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
|
||||
/// specifies a shuffle of elements that is suitable for input to MOVDDUP.
|
||||
bool isMOVDDUPMask(ShuffleVectorSDNode *N);
|
||||
bool isMOVDDUPMask(SDNode *N);
|
||||
|
||||
/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
|
||||
/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
|
||||
@ -470,13 +477,14 @@ namespace llvm {
|
||||
/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
|
||||
/// By default, if a target supports the VECTOR_SHUFFLE node, all mask
|
||||
/// values are assumed to be legal.
|
||||
virtual bool isShuffleMaskLegal(const int *Mask, MVT VT) const;
|
||||
virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const;
|
||||
|
||||
/// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
|
||||
/// used by Targets can use this to indicate if there is a suitable
|
||||
/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
|
||||
/// pool entry.
|
||||
virtual bool isVectorClearMaskLegal(const int *Mask, MVT VT) const;
|
||||
virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
|
||||
MVT EVT, SelectionDAG &DAG) const;
|
||||
|
||||
/// ShouldShrinkFPConstant - If true, then instruction selection should
|
||||
/// seek to shrink the FP constant of the specified type to a smaller type
|
||||
|
@ -3801,7 +3801,6 @@ def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
|
||||
(implicit EFLAGS)),
|
||||
(DEC32m addr:$dst)>, Requires<[In32BitMode]>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating Point Stack Support
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
@ -30,37 +30,33 @@ def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
|
||||
|
||||
// MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
|
||||
// PSHUFW imm.
|
||||
def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
|
||||
def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
|
||||
return getI8Imm(X86::getShuffleSHUFImmediate(N));
|
||||
}]>;
|
||||
|
||||
// Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
|
||||
def mmx_unpckh : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
|
||||
def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isUNPCKHMask(N);
|
||||
}]>;
|
||||
|
||||
// Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
|
||||
def mmx_unpckl : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
|
||||
def MMX_UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isUNPCKLMask(N);
|
||||
}]>;
|
||||
|
||||
// Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
|
||||
def mmx_unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
|
||||
def MMX_UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isUNPCKH_v_undef_Mask(N);
|
||||
}]>;
|
||||
|
||||
// Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
|
||||
def mmx_unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
|
||||
def MMX_UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isUNPCKL_v_undef_Mask(N);
|
||||
}]>;
|
||||
|
||||
def mmx_pshufw : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
|
||||
// Patterns for shuffling.
|
||||
def MMX_PSHUFW_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isPSHUFDMask(N);
|
||||
}], MMX_SHUFFLE_get_shuf_imm>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -189,8 +185,9 @@ def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
|
||||
def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
|
||||
"movq2dq\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(movl immAllZerosV,
|
||||
(v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src))))))]>;
|
||||
(v2i64 (vector_shuffle immAllZerosV,
|
||||
(v2i64 (scalar_to_vector (i64 (bitconvert VR64:$src)))),
|
||||
MOVL_shuffle_mask)))]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMDestMem, (outs FR64:$dst), (ins VR64:$src),
|
||||
@ -322,74 +319,86 @@ let isTwoAddress = 1 in {
|
||||
(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
|
||||
"punpckhbw\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(v8i8 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
|
||||
(v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
|
||||
MMX_UNPCKH_shuffle_mask)))]>;
|
||||
def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
|
||||
(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
|
||||
"punpckhbw\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(v8i8 (mmx_unpckh VR64:$src1,
|
||||
(bc_v8i8 (load_mmx addr:$src2)))))]>;
|
||||
(v8i8 (vector_shuffle VR64:$src1,
|
||||
(bc_v8i8 (load_mmx addr:$src2)),
|
||||
MMX_UNPCKH_shuffle_mask)))]>;
|
||||
|
||||
def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
|
||||
(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
|
||||
"punpckhwd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(v4i16 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
|
||||
(v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
|
||||
MMX_UNPCKH_shuffle_mask)))]>;
|
||||
def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
|
||||
(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
|
||||
"punpckhwd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(v4i16 (mmx_unpckh VR64:$src1,
|
||||
(bc_v4i16 (load_mmx addr:$src2)))))]>;
|
||||
(v4i16 (vector_shuffle VR64:$src1,
|
||||
(bc_v4i16 (load_mmx addr:$src2)),
|
||||
MMX_UNPCKH_shuffle_mask)))]>;
|
||||
|
||||
def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
|
||||
(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
|
||||
"punpckhdq\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(v2i32 (mmx_unpckh VR64:$src1, VR64:$src2)))]>;
|
||||
(v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
|
||||
MMX_UNPCKH_shuffle_mask)))]>;
|
||||
def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
|
||||
(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
|
||||
"punpckhdq\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(v2i32 (mmx_unpckh VR64:$src1,
|
||||
(bc_v2i32 (load_mmx addr:$src2)))))]>;
|
||||
(v2i32 (vector_shuffle VR64:$src1,
|
||||
(bc_v2i32 (load_mmx addr:$src2)),
|
||||
MMX_UNPCKH_shuffle_mask)))]>;
|
||||
|
||||
// Unpack Low Packed Data Instructions
|
||||
def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
|
||||
(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
|
||||
"punpcklbw\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(v8i8 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
|
||||
(v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
|
||||
MMX_UNPCKL_shuffle_mask)))]>;
|
||||
def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
|
||||
(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
|
||||
"punpcklbw\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(v8i8 (mmx_unpckl VR64:$src1,
|
||||
(bc_v8i8 (load_mmx addr:$src2)))))]>;
|
||||
(v8i8 (vector_shuffle VR64:$src1,
|
||||
(bc_v8i8 (load_mmx addr:$src2)),
|
||||
MMX_UNPCKL_shuffle_mask)))]>;
|
||||
|
||||
def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
|
||||
(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
|
||||
"punpcklwd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(v4i16 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
|
||||
(v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
|
||||
MMX_UNPCKL_shuffle_mask)))]>;
|
||||
def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
|
||||
(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
|
||||
"punpcklwd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(v4i16 (mmx_unpckl VR64:$src1,
|
||||
(bc_v4i16 (load_mmx addr:$src2)))))]>;
|
||||
(v4i16 (vector_shuffle VR64:$src1,
|
||||
(bc_v4i16 (load_mmx addr:$src2)),
|
||||
MMX_UNPCKL_shuffle_mask)))]>;
|
||||
|
||||
def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
|
||||
(outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
|
||||
"punpckldq\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(v2i32 (mmx_unpckl VR64:$src1, VR64:$src2)))]>;
|
||||
(v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
|
||||
MMX_UNPCKL_shuffle_mask)))]>;
|
||||
def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
|
||||
(outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
|
||||
"punpckldq\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(v2i32 (mmx_unpckl VR64:$src1,
|
||||
(bc_v2i32 (load_mmx addr:$src2)))))]>;
|
||||
(v2i32 (vector_shuffle VR64:$src1,
|
||||
(bc_v2i32 (load_mmx addr:$src2)),
|
||||
MMX_UNPCKL_shuffle_mask)))]>;
|
||||
}
|
||||
|
||||
// -- Pack Instructions
|
||||
@ -402,13 +411,17 @@ def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
|
||||
(outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
|
||||
"pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(v4i16 (mmx_pshufw:$src2 VR64:$src1, (undef))))]>;
|
||||
(v4i16 (vector_shuffle
|
||||
VR64:$src1, (undef),
|
||||
MMX_PSHUFW_shuffle_mask:$src2)))]>;
|
||||
def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
|
||||
(outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
|
||||
"pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set VR64:$dst,
|
||||
(mmx_pshufw:$src2 (bc_v4i16 (load_mmx addr:$src1)),
|
||||
(undef)))]>;
|
||||
(v4i16 (vector_shuffle
|
||||
(bc_v4i16 (load_mmx addr:$src1)),
|
||||
(undef),
|
||||
MMX_PSHUFW_shuffle_mask:$src2)))]>;
|
||||
|
||||
// -- Conversion Instructions
|
||||
let neverHasSideEffects = 1 in {
|
||||
@ -614,27 +627,34 @@ def : Pat<(bc_v4i16 (v2i32 (scalar_to_vector GR32:$src))),
|
||||
|
||||
// Patterns to perform canonical versions of vector shuffling.
|
||||
let AddedComplexity = 10 in {
|
||||
def : Pat<(v8i8 (mmx_unpckl_undef VR64:$src, (undef))),
|
||||
def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
|
||||
MMX_UNPCKL_v_undef_shuffle_mask)),
|
||||
(MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
|
||||
def : Pat<(v4i16 (mmx_unpckl_undef VR64:$src, (undef))),
|
||||
def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
|
||||
MMX_UNPCKL_v_undef_shuffle_mask)),
|
||||
(MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
|
||||
def : Pat<(v2i32 (mmx_unpckl_undef VR64:$src, (undef))),
|
||||
def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
|
||||
MMX_UNPCKL_v_undef_shuffle_mask)),
|
||||
(MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
|
||||
}
|
||||
|
||||
let AddedComplexity = 10 in {
|
||||
def : Pat<(v8i8 (mmx_unpckh_undef VR64:$src, (undef))),
|
||||
def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
|
||||
MMX_UNPCKH_v_undef_shuffle_mask)),
|
||||
(MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
|
||||
def : Pat<(v4i16 (mmx_unpckh_undef VR64:$src, (undef))),
|
||||
def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
|
||||
MMX_UNPCKH_v_undef_shuffle_mask)),
|
||||
(MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
|
||||
def : Pat<(v2i32 (mmx_unpckh_undef VR64:$src, (undef))),
|
||||
def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
|
||||
MMX_UNPCKH_v_undef_shuffle_mask)),
|
||||
(MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
|
||||
}
|
||||
|
||||
// Patterns to perform vector shuffling with a zeroed out vector.
|
||||
let AddedComplexity = 20 in {
|
||||
def : Pat<(bc_v2i32 (mmx_unpckl immAllZerosV,
|
||||
(v2i32 (scalar_to_vector (load_mmx addr:$src))))),
|
||||
def : Pat<(bc_v2i32 (vector_shuffle immAllZerosV,
|
||||
(v2i32 (scalar_to_vector (load_mmx addr:$src))),
|
||||
MMX_UNPCKL_shuffle_mask)),
|
||||
(MMX_PUNPCKLDQrm VR64:$src, VR64:$src)>;
|
||||
}
|
||||
|
||||
|
@ -175,108 +175,103 @@ def PSxLDQ_imm : SDNodeXForm<imm, [{
|
||||
|
||||
// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
|
||||
// SHUFP* etc. imm.
|
||||
def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
|
||||
def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
|
||||
return getI8Imm(X86::getShuffleSHUFImmediate(N));
|
||||
}]>;
|
||||
|
||||
// SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
|
||||
// PSHUFHW imm.
|
||||
def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
|
||||
def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
|
||||
return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
|
||||
}]>;
|
||||
|
||||
// SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
|
||||
// PSHUFLW imm.
|
||||
def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
|
||||
def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
|
||||
return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
|
||||
}]>;
|
||||
|
||||
def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
|
||||
return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
|
||||
}]>;
|
||||
|
||||
def movddup : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
|
||||
}]>;
|
||||
|
||||
def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
|
||||
}]>;
|
||||
|
||||
def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
|
||||
}]>;
|
||||
|
||||
def movhp : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isMOVHPMask(cast<ShuffleVectorSDNode>(N));
|
||||
}]>;
|
||||
|
||||
def movlp : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
|
||||
}]>;
|
||||
|
||||
def movl : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
|
||||
}]>;
|
||||
|
||||
def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
|
||||
}]>;
|
||||
|
||||
def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
|
||||
}]>;
|
||||
|
||||
def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
|
||||
}]>;
|
||||
|
||||
def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
|
||||
}]>;
|
||||
|
||||
def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
|
||||
}]>;
|
||||
|
||||
def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
|
||||
}]>;
|
||||
|
||||
def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
|
||||
def SSE_splat_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isSplatMask(N);
|
||||
}], SHUFFLE_get_shuf_imm>;
|
||||
|
||||
def shufp : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
|
||||
def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isSplatLoMask(N);
|
||||
}]>;
|
||||
|
||||
def MOVDDUP_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isMOVDDUPMask(N);
|
||||
}]>;
|
||||
|
||||
def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isMOVHLPSMask(N);
|
||||
}]>;
|
||||
|
||||
def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isMOVHLPS_v_undef_Mask(N);
|
||||
}]>;
|
||||
|
||||
def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isMOVHPMask(N);
|
||||
}]>;
|
||||
|
||||
def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isMOVLPMask(N);
|
||||
}]>;
|
||||
|
||||
def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isMOVLMask(N);
|
||||
}]>;
|
||||
|
||||
def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isMOVSHDUPMask(N);
|
||||
}]>;
|
||||
|
||||
def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isMOVSLDUPMask(N);
|
||||
}]>;
|
||||
|
||||
def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isUNPCKLMask(N);
|
||||
}]>;
|
||||
|
||||
def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isUNPCKHMask(N);
|
||||
}]>;
|
||||
|
||||
def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isUNPCKL_v_undef_Mask(N);
|
||||
}]>;
|
||||
|
||||
def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isUNPCKH_v_undef_Mask(N);
|
||||
}]>;
|
||||
|
||||
def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isPSHUFDMask(N);
|
||||
}], SHUFFLE_get_shuf_imm>;
|
||||
|
||||
def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
|
||||
def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isPSHUFHWMask(N);
|
||||
}], SHUFFLE_get_pshufhw_imm>;
|
||||
|
||||
def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
|
||||
(vector_shuffle node:$lhs, node:$rhs), [{
|
||||
return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
|
||||
def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isPSHUFLWMask(N);
|
||||
}], SHUFFLE_get_pshuflw_imm>;
|
||||
|
||||
def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isPSHUFDMask(N);
|
||||
}], SHUFFLE_get_shuf_imm>;
|
||||
|
||||
def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isSHUFPMask(N);
|
||||
}], SHUFFLE_get_shuf_imm>;
|
||||
|
||||
def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
|
||||
return X86::isSHUFPMask(N);
|
||||
}], SHUFFLE_get_shuf_imm>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SSE scalar FP Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -709,14 +704,16 @@ let Constraints = "$src1 = $dst" in {
|
||||
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
|
||||
"movlps\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(movlp VR128:$src1,
|
||||
(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
|
||||
(v4f32 (vector_shuffle VR128:$src1,
|
||||
(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
|
||||
MOVLP_shuffle_mask)))]>;
|
||||
def MOVHPSrm : PSI<0x16, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
|
||||
"movhps\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(movhp VR128:$src1,
|
||||
(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
|
||||
(v4f32 (vector_shuffle VR128:$src1,
|
||||
(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
|
||||
MOVHP_shuffle_mask)))]>;
|
||||
} // AddedComplexity
|
||||
} // Constraints = "$src1 = $dst"
|
||||
|
||||
@ -731,25 +728,29 @@ def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
|
||||
def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
|
||||
"movhps\t{$src, $dst|$dst, $src}",
|
||||
[(store (f64 (vector_extract
|
||||
(unpckh (bc_v2f64 (v4f32 VR128:$src)),
|
||||
(undef)), (iPTR 0))), addr:$dst)]>;
|
||||
(v2f64 (vector_shuffle
|
||||
(bc_v2f64 (v4f32 VR128:$src)), (undef),
|
||||
UNPCKH_shuffle_mask)), (iPTR 0))),
|
||||
addr:$dst)]>;
|
||||
|
||||
let Constraints = "$src1 = $dst" in {
|
||||
let AddedComplexity = 20 in {
|
||||
def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"movlhps\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v4f32 (movhp VR128:$src1, VR128:$src2)))]>;
|
||||
(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
MOVHP_shuffle_mask)))]>;
|
||||
|
||||
def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"movhlps\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
|
||||
(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
MOVHLPS_shuffle_mask)))]>;
|
||||
} // AddedComplexity
|
||||
} // Constraints = "$src1 = $dst"
|
||||
|
||||
let AddedComplexity = 20 in
|
||||
def : Pat<(v4f32 (movddup VR128:$src, (undef))),
|
||||
def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), MOVDDUP_shuffle_mask)),
|
||||
(MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
|
||||
|
||||
|
||||
@ -907,41 +908,51 @@ let Constraints = "$src1 = $dst" in {
|
||||
let isConvertibleToThreeAddress = 1 in // Convert to pshufd
|
||||
def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1,
|
||||
VR128:$src2, i8imm:$src3),
|
||||
VR128:$src2, i32i8imm:$src3),
|
||||
"shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||
[(set VR128:$dst,
|
||||
(v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
|
||||
(v4f32 (vector_shuffle
|
||||
VR128:$src1, VR128:$src2,
|
||||
SHUFP_shuffle_mask:$src3)))]>;
|
||||
def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1,
|
||||
f128mem:$src2, i8imm:$src3),
|
||||
f128mem:$src2, i32i8imm:$src3),
|
||||
"shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||
[(set VR128:$dst,
|
||||
(v4f32 (shufp:$src3
|
||||
VR128:$src1, (memopv4f32 addr:$src2))))]>;
|
||||
(v4f32 (vector_shuffle
|
||||
VR128:$src1, (memopv4f32 addr:$src2),
|
||||
SHUFP_shuffle_mask:$src3)))]>;
|
||||
|
||||
let AddedComplexity = 10 in {
|
||||
def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"unpckhps\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
|
||||
(v4f32 (vector_shuffle
|
||||
VR128:$src1, VR128:$src2,
|
||||
UNPCKH_shuffle_mask)))]>;
|
||||
def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
||||
"unpckhps\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v4f32 (unpckh VR128:$src1,
|
||||
(memopv4f32 addr:$src2))))]>;
|
||||
(v4f32 (vector_shuffle
|
||||
VR128:$src1, (memopv4f32 addr:$src2),
|
||||
UNPCKH_shuffle_mask)))]>;
|
||||
|
||||
def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"unpcklps\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
|
||||
(v4f32 (vector_shuffle
|
||||
VR128:$src1, VR128:$src2,
|
||||
UNPCKL_shuffle_mask)))]>;
|
||||
def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
||||
"unpcklps\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
|
||||
(v4f32 (vector_shuffle
|
||||
VR128:$src1, (memopv4f32 addr:$src2),
|
||||
UNPCKL_shuffle_mask)))]>;
|
||||
} // AddedComplexity
|
||||
} // Constraints = "$src1 = $dst"
|
||||
|
||||
@ -1033,7 +1044,8 @@ let neverHasSideEffects = 1 in
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"movss\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v4f32 (movl VR128:$src1, VR128:$src2)))]>;
|
||||
(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
MOVL_shuffle_mask)))]>;
|
||||
}
|
||||
|
||||
// Move to lower bits of a VR128 and zeroing upper bits.
|
||||
@ -1439,14 +1451,16 @@ let Constraints = "$src1 = $dst" in {
|
||||
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
|
||||
"movlpd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v2f64 (movlp VR128:$src1,
|
||||
(scalar_to_vector (loadf64 addr:$src2)))))]>;
|
||||
(v2f64 (vector_shuffle VR128:$src1,
|
||||
(scalar_to_vector (loadf64 addr:$src2)),
|
||||
MOVLP_shuffle_mask)))]>;
|
||||
def MOVHPDrm : PDI<0x16, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
|
||||
"movhpd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v2f64 (movhp VR128:$src1,
|
||||
(scalar_to_vector (loadf64 addr:$src2)))))]>;
|
||||
(v2f64 (vector_shuffle VR128:$src1,
|
||||
(scalar_to_vector (loadf64 addr:$src2)),
|
||||
MOVHP_shuffle_mask)))]>;
|
||||
} // AddedComplexity
|
||||
} // Constraints = "$src1 = $dst"
|
||||
|
||||
@ -1460,8 +1474,9 @@ def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
|
||||
def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
|
||||
"movhpd\t{$src, $dst|$dst, $src}",
|
||||
[(store (f64 (vector_extract
|
||||
(v2f64 (unpckh VR128:$src, (undef))),
|
||||
(iPTR 0))), addr:$dst)]>;
|
||||
(v2f64 (vector_shuffle VR128:$src, (undef),
|
||||
UNPCKH_shuffle_mask)), (iPTR 0))),
|
||||
addr:$dst)]>;
|
||||
|
||||
// SSE2 instructions without OpSize prefix
|
||||
def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
@ -1729,39 +1744,48 @@ let Constraints = "$src1 = $dst" in {
|
||||
def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
|
||||
"shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||
[(set VR128:$dst,
|
||||
(v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
|
||||
[(set VR128:$dst, (v2f64 (vector_shuffle
|
||||
VR128:$src1, VR128:$src2,
|
||||
SHUFP_shuffle_mask:$src3)))]>;
|
||||
def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1,
|
||||
f128mem:$src2, i8imm:$src3),
|
||||
"shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||
[(set VR128:$dst,
|
||||
(v2f64 (shufp:$src3
|
||||
VR128:$src1, (memopv2f64 addr:$src2))))]>;
|
||||
(v2f64 (vector_shuffle
|
||||
VR128:$src1, (memopv2f64 addr:$src2),
|
||||
SHUFP_shuffle_mask:$src3)))]>;
|
||||
|
||||
let AddedComplexity = 10 in {
|
||||
def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"unpckhpd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
|
||||
(v2f64 (vector_shuffle
|
||||
VR128:$src1, VR128:$src2,
|
||||
UNPCKH_shuffle_mask)))]>;
|
||||
def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
||||
"unpckhpd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v2f64 (unpckh VR128:$src1,
|
||||
(memopv2f64 addr:$src2))))]>;
|
||||
(v2f64 (vector_shuffle
|
||||
VR128:$src1, (memopv2f64 addr:$src2),
|
||||
UNPCKH_shuffle_mask)))]>;
|
||||
|
||||
def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"unpcklpd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
|
||||
(v2f64 (vector_shuffle
|
||||
VR128:$src1, VR128:$src2,
|
||||
UNPCKL_shuffle_mask)))]>;
|
||||
def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
||||
"unpcklpd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
|
||||
(v2f64 (vector_shuffle
|
||||
VR128:$src1, (memopv2f64 addr:$src2),
|
||||
UNPCKL_shuffle_mask)))]>;
|
||||
} // AddedComplexity
|
||||
} // Constraints = "$src1 = $dst"
|
||||
|
||||
@ -2019,43 +2043,49 @@ defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
|
||||
def PSHUFDri : PDIi8<0x70, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
|
||||
"pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set VR128:$dst, (v4i32 (pshufd:$src2
|
||||
VR128:$src1, (undef))))]>;
|
||||
[(set VR128:$dst, (v4i32 (vector_shuffle
|
||||
VR128:$src1, (undef),
|
||||
PSHUFD_shuffle_mask:$src2)))]>;
|
||||
def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
|
||||
"pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set VR128:$dst, (v4i32 (pshufd:$src2
|
||||
[(set VR128:$dst, (v4i32 (vector_shuffle
|
||||
(bc_v4i32(memopv2i64 addr:$src1)),
|
||||
(undef))))]>;
|
||||
(undef),
|
||||
PSHUFD_shuffle_mask:$src2)))]>;
|
||||
|
||||
// SSE2 with ImmT == Imm8 and XS prefix.
|
||||
def PSHUFHWri : Ii8<0x70, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
|
||||
"pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
|
||||
(undef))))]>,
|
||||
[(set VR128:$dst, (v8i16 (vector_shuffle
|
||||
VR128:$src1, (undef),
|
||||
PSHUFHW_shuffle_mask:$src2)))]>,
|
||||
XS, Requires<[HasSSE2]>;
|
||||
def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
|
||||
"pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set VR128:$dst, (v8i16 (pshufhw:$src2
|
||||
(bc_v8i16 (memopv2i64 addr:$src1)),
|
||||
(undef))))]>,
|
||||
[(set VR128:$dst, (v8i16 (vector_shuffle
|
||||
(bc_v8i16 (memopv2i64 addr:$src1)),
|
||||
(undef),
|
||||
PSHUFHW_shuffle_mask:$src2)))]>,
|
||||
XS, Requires<[HasSSE2]>;
|
||||
|
||||
// SSE2 with ImmT == Imm8 and XD prefix.
|
||||
def PSHUFLWri : Ii8<0x70, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
|
||||
(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
|
||||
"pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
|
||||
(undef))))]>,
|
||||
[(set VR128:$dst, (v8i16 (vector_shuffle
|
||||
VR128:$src1, (undef),
|
||||
PSHUFLW_shuffle_mask:$src2)))]>,
|
||||
XD, Requires<[HasSSE2]>;
|
||||
def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
|
||||
(outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
|
||||
"pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
[(set VR128:$dst, (v8i16 (pshuflw:$src2
|
||||
(bc_v8i16 (memopv2i64 addr:$src1)),
|
||||
(undef))))]>,
|
||||
[(set VR128:$dst, (v8i16 (vector_shuffle
|
||||
(bc_v8i16 (memopv2i64 addr:$src1)),
|
||||
(undef),
|
||||
PSHUFLW_shuffle_mask:$src2)))]>,
|
||||
XD, Requires<[HasSSE2]>;
|
||||
|
||||
|
||||
@ -2064,91 +2094,107 @@ let Constraints = "$src1 = $dst" in {
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"punpcklbw\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v16i8 (unpckl VR128:$src1, VR128:$src2)))]>;
|
||||
(v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
UNPCKL_shuffle_mask)))]>;
|
||||
def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
||||
"punpcklbw\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(unpckl VR128:$src1,
|
||||
(bc_v16i8 (memopv2i64 addr:$src2))))]>;
|
||||
(v16i8 (vector_shuffle VR128:$src1,
|
||||
(bc_v16i8 (memopv2i64 addr:$src2)),
|
||||
UNPCKL_shuffle_mask)))]>;
|
||||
def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"punpcklwd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v8i16 (unpckl VR128:$src1, VR128:$src2)))]>;
|
||||
(v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
UNPCKL_shuffle_mask)))]>;
|
||||
def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
||||
"punpcklwd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(unpckl VR128:$src1,
|
||||
(bc_v8i16 (memopv2i64 addr:$src2))))]>;
|
||||
(v8i16 (vector_shuffle VR128:$src1,
|
||||
(bc_v8i16 (memopv2i64 addr:$src2)),
|
||||
UNPCKL_shuffle_mask)))]>;
|
||||
def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"punpckldq\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v4i32 (unpckl VR128:$src1, VR128:$src2)))]>;
|
||||
(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
UNPCKL_shuffle_mask)))]>;
|
||||
def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
||||
"punpckldq\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(unpckl VR128:$src1,
|
||||
(bc_v4i32 (memopv2i64 addr:$src2))))]>;
|
||||
(v4i32 (vector_shuffle VR128:$src1,
|
||||
(bc_v4i32 (memopv2i64 addr:$src2)),
|
||||
UNPCKL_shuffle_mask)))]>;
|
||||
def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"punpcklqdq\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
|
||||
(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
UNPCKL_shuffle_mask)))]>;
|
||||
def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
||||
"punpcklqdq\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v2i64 (unpckl VR128:$src1,
|
||||
(memopv2i64 addr:$src2))))]>;
|
||||
(v2i64 (vector_shuffle VR128:$src1,
|
||||
(memopv2i64 addr:$src2),
|
||||
UNPCKL_shuffle_mask)))]>;
|
||||
|
||||
def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"punpckhbw\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v16i8 (unpckh VR128:$src1, VR128:$src2)))]>;
|
||||
(v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
UNPCKH_shuffle_mask)))]>;
|
||||
def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
||||
"punpckhbw\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(unpckh VR128:$src1,
|
||||
(bc_v16i8 (memopv2i64 addr:$src2))))]>;
|
||||
[(set VR128:$dst,
|
||||
(v16i8 (vector_shuffle VR128:$src1,
|
||||
(bc_v16i8 (memopv2i64 addr:$src2)),
|
||||
UNPCKH_shuffle_mask)))]>;
|
||||
def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"punpckhwd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v8i16 (unpckh VR128:$src1, VR128:$src2)))]>;
|
||||
(v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
UNPCKH_shuffle_mask)))]>;
|
||||
def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
||||
"punpckhwd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(unpckh VR128:$src1,
|
||||
(bc_v8i16 (memopv2i64 addr:$src2))))]>;
|
||||
(v8i16 (vector_shuffle VR128:$src1,
|
||||
(bc_v8i16 (memopv2i64 addr:$src2)),
|
||||
UNPCKH_shuffle_mask)))]>;
|
||||
def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"punpckhdq\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v4i32 (unpckh VR128:$src1, VR128:$src2)))]>;
|
||||
(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
UNPCKH_shuffle_mask)))]>;
|
||||
def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
||||
"punpckhdq\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(unpckh VR128:$src1,
|
||||
(bc_v4i32 (memopv2i64 addr:$src2))))]>;
|
||||
(v4i32 (vector_shuffle VR128:$src1,
|
||||
(bc_v4i32 (memopv2i64 addr:$src2)),
|
||||
UNPCKH_shuffle_mask)))]>;
|
||||
def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"punpckhqdq\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
|
||||
(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
UNPCKH_shuffle_mask)))]>;
|
||||
def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
|
||||
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
||||
"punpckhqdq\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v2i64 (unpckh VR128:$src1,
|
||||
(memopv2i64 addr:$src2))))]>;
|
||||
(v2i64 (vector_shuffle VR128:$src1,
|
||||
(memopv2i64 addr:$src2),
|
||||
UNPCKH_shuffle_mask)))]>;
|
||||
}
|
||||
|
||||
// Extract / Insert
|
||||
@ -2311,7 +2357,8 @@ let Constraints = "$src1 = $dst" in {
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"movsd\t{$src2, $dst|$dst, $src2}",
|
||||
[(set VR128:$dst,
|
||||
(v2f64 (movl VR128:$src1, VR128:$src2)))]>;
|
||||
(v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
MOVL_shuffle_mask)))]>;
|
||||
}
|
||||
|
||||
// Store / copy lower 64-bits of a XMM register.
|
||||
@ -2402,35 +2449,44 @@ def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
|
||||
// Move Instructions
|
||||
def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"movshdup\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (v4f32 (movshdup
|
||||
VR128:$src, (undef))))]>;
|
||||
[(set VR128:$dst, (v4f32 (vector_shuffle
|
||||
VR128:$src, (undef),
|
||||
MOVSHDUP_shuffle_mask)))]>;
|
||||
def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
||||
"movshdup\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (movshdup
|
||||
(memopv4f32 addr:$src), (undef)))]>;
|
||||
[(set VR128:$dst, (v4f32 (vector_shuffle
|
||||
(memopv4f32 addr:$src), (undef),
|
||||
MOVSHDUP_shuffle_mask)))]>;
|
||||
|
||||
def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"movsldup\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (v4f32 (movsldup
|
||||
VR128:$src, (undef))))]>;
|
||||
[(set VR128:$dst, (v4f32 (vector_shuffle
|
||||
VR128:$src, (undef),
|
||||
MOVSLDUP_shuffle_mask)))]>;
|
||||
def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
||||
"movsldup\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (movsldup
|
||||
(memopv4f32 addr:$src), (undef)))]>;
|
||||
[(set VR128:$dst, (v4f32 (vector_shuffle
|
||||
(memopv4f32 addr:$src), (undef),
|
||||
MOVSLDUP_shuffle_mask)))]>;
|
||||
|
||||
def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
||||
"movddup\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
|
||||
[(set VR128:$dst,
|
||||
(v2f64 (vector_shuffle VR128:$src, (undef),
|
||||
MOVDDUP_shuffle_mask)))]>;
|
||||
def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
|
||||
"movddup\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst,
|
||||
(v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
|
||||
(undef))))]>;
|
||||
(v2f64 (vector_shuffle
|
||||
(scalar_to_vector (loadf64 addr:$src)),
|
||||
(undef), MOVDDUP_shuffle_mask)))]>;
|
||||
|
||||
def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
|
||||
(undef)),
|
||||
def : Pat<(vector_shuffle
|
||||
(bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
|
||||
(undef), MOVDDUP_shuffle_mask),
|
||||
(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
|
||||
def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
|
||||
def : Pat<(vector_shuffle
|
||||
(memopv2f64 addr:$src), (undef), MOVDDUP_shuffle_mask),
|
||||
(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
|
||||
|
||||
|
||||
@ -2499,18 +2555,22 @@ def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
|
||||
|
||||
// vector_shuffle v1, <undef> <1, 1, 3, 3>
|
||||
let AddedComplexity = 15 in
|
||||
def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
|
||||
MOVSHDUP_shuffle_mask)),
|
||||
(MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
|
||||
let AddedComplexity = 20 in
|
||||
def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
|
||||
def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
|
||||
MOVSHDUP_shuffle_mask)),
|
||||
(MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
|
||||
|
||||
// vector_shuffle v1, <undef> <0, 0, 2, 2>
|
||||
let AddedComplexity = 15 in
|
||||
def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
|
||||
MOVSLDUP_shuffle_mask)),
|
||||
(MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
|
||||
let AddedComplexity = 20 in
|
||||
def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
|
||||
def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
|
||||
MOVSLDUP_shuffle_mask)),
|
||||
(MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -2851,173 +2911,207 @@ def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
|
||||
|
||||
// Splat v2f64 / v2i64
|
||||
let AddedComplexity = 10 in {
|
||||
def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
|
||||
def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
|
||||
(UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
|
||||
def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
|
||||
(UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
|
||||
def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
|
||||
(PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
|
||||
def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
|
||||
(PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
||||
}
|
||||
|
||||
// Special unary SHUFPSrri case.
|
||||
def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
|
||||
(SHUFPSrri VR128:$src1, VR128:$src1,
|
||||
(SHUFFLE_get_shuf_imm VR128:$src3))>,
|
||||
def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
|
||||
SHUFP_unary_shuffle_mask:$sm)),
|
||||
(SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
|
||||
Requires<[HasSSE1]>;
|
||||
let AddedComplexity = 5 in
|
||||
def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
|
||||
(PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
|
||||
Requires<[HasSSE2]>;
|
||||
// Special unary SHUFPDrri case.
|
||||
def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
|
||||
(SHUFPDrri VR128:$src1, VR128:$src1,
|
||||
(SHUFFLE_get_shuf_imm VR128:$src3))>,
|
||||
Requires<[HasSSE2]>;
|
||||
// Special unary SHUFPDrri case.
|
||||
def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
|
||||
(SHUFPDrri VR128:$src1, VR128:$src1,
|
||||
(SHUFFLE_get_shuf_imm VR128:$src3))>,
|
||||
def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
|
||||
SHUFP_unary_shuffle_mask:$sm)),
|
||||
(SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
|
||||
Requires<[HasSSE2]>;
|
||||
// Unary v4f32 shuffle with PSHUF* in order to fold a load.
|
||||
def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
|
||||
(PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
|
||||
def : Pat<(vector_shuffle (bc_v4i32 (memopv4f32 addr:$src1)), (undef),
|
||||
SHUFP_unary_shuffle_mask:$sm),
|
||||
(PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
|
||||
Requires<[HasSSE2]>;
|
||||
|
||||
// Special binary v4i32 shuffle cases with SHUFPS.
|
||||
def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
|
||||
(SHUFPSrri VR128:$src1, VR128:$src2,
|
||||
(SHUFFLE_get_shuf_imm VR128:$src3))>,
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
|
||||
PSHUFD_binary_shuffle_mask:$sm)),
|
||||
(SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
|
||||
Requires<[HasSSE2]>;
|
||||
def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
|
||||
(SHUFPSrmi VR128:$src1, addr:$src2,
|
||||
(SHUFFLE_get_shuf_imm VR128:$src3))>,
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src1,
|
||||
(bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
|
||||
(SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
|
||||
Requires<[HasSSE2]>;
|
||||
// Special binary v2i64 shuffle cases using SHUFPDrri.
|
||||
def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
|
||||
(SHUFPDrri VR128:$src1, VR128:$src2,
|
||||
(SHUFFLE_get_shuf_imm VR128:$src3))>,
|
||||
def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
SHUFP_shuffle_mask:$sm)),
|
||||
(SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
|
||||
Requires<[HasSSE2]>;
|
||||
// Special unary SHUFPDrri case.
|
||||
def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
|
||||
SHUFP_unary_shuffle_mask:$sm)),
|
||||
(SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
|
||||
Requires<[HasSSE2]>;
|
||||
|
||||
// vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
|
||||
let AddedComplexity = 15 in {
|
||||
def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
|
||||
(PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
|
||||
UNPCKL_v_undef_shuffle_mask:$sm)),
|
||||
(PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
|
||||
Requires<[OptForSpeed, HasSSE2]>;
|
||||
def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
|
||||
(PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
|
||||
def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
|
||||
UNPCKL_v_undef_shuffle_mask:$sm)),
|
||||
(PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
|
||||
Requires<[OptForSpeed, HasSSE2]>;
|
||||
}
|
||||
let AddedComplexity = 10 in {
|
||||
def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
|
||||
def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
|
||||
UNPCKL_v_undef_shuffle_mask)),
|
||||
(UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
|
||||
def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
|
||||
def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
|
||||
UNPCKL_v_undef_shuffle_mask)),
|
||||
(PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
|
||||
def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
|
||||
UNPCKL_v_undef_shuffle_mask)),
|
||||
(PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
|
||||
UNPCKL_v_undef_shuffle_mask)),
|
||||
(PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
||||
}
|
||||
|
||||
// vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
|
||||
let AddedComplexity = 15 in {
|
||||
def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
|
||||
(PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
|
||||
UNPCKH_v_undef_shuffle_mask:$sm)),
|
||||
(PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
|
||||
Requires<[OptForSpeed, HasSSE2]>;
|
||||
def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
|
||||
(PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
|
||||
def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
|
||||
UNPCKH_v_undef_shuffle_mask:$sm)),
|
||||
(PSHUFDri VR128:$src, PSHUFD_shuffle_mask:$sm)>,
|
||||
Requires<[OptForSpeed, HasSSE2]>;
|
||||
}
|
||||
let AddedComplexity = 10 in {
|
||||
def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
|
||||
def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
|
||||
UNPCKH_v_undef_shuffle_mask)),
|
||||
(UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
|
||||
def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
|
||||
def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
|
||||
UNPCKH_v_undef_shuffle_mask)),
|
||||
(PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
|
||||
def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
|
||||
UNPCKH_v_undef_shuffle_mask)),
|
||||
(PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
|
||||
UNPCKH_v_undef_shuffle_mask)),
|
||||
(PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
||||
}
|
||||
|
||||
let AddedComplexity = 20 in {
|
||||
// vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
|
||||
def : Pat<(v4i32 (movhp VR128:$src1, VR128:$src2)),
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
MOVHP_shuffle_mask)),
|
||||
(MOVLHPSrr VR128:$src1, VR128:$src2)>;
|
||||
|
||||
// vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
|
||||
def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
MOVHLPS_shuffle_mask)),
|
||||
(MOVHLPSrr VR128:$src1, VR128:$src2)>;
|
||||
|
||||
// vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
|
||||
def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
|
||||
def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
|
||||
MOVHLPS_v_undef_shuffle_mask)),
|
||||
(MOVHLPSrr VR128:$src1, VR128:$src1)>;
|
||||
def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
|
||||
MOVHLPS_v_undef_shuffle_mask)),
|
||||
(MOVHLPSrr VR128:$src1, VR128:$src1)>;
|
||||
}
|
||||
|
||||
let AddedComplexity = 20 in {
|
||||
// vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
|
||||
// vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
|
||||
def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
|
||||
def : Pat<(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
|
||||
MOVLP_shuffle_mask)),
|
||||
(MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
|
||||
def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
|
||||
def : Pat<(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
|
||||
MOVLP_shuffle_mask)),
|
||||
(MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v4f32 (movhp VR128:$src1, (load addr:$src2))),
|
||||
def : Pat<(v4f32 (vector_shuffle VR128:$src1, (load addr:$src2),
|
||||
MOVHP_shuffle_mask)),
|
||||
(MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
|
||||
def : Pat<(v2f64 (movhp VR128:$src1, (load addr:$src2))),
|
||||
def : Pat<(v2f64 (vector_shuffle VR128:$src1, (load addr:$src2),
|
||||
MOVHP_shuffle_mask)),
|
||||
(MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
||||
|
||||
def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
|
||||
MOVLP_shuffle_mask)),
|
||||
(MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
|
||||
def : Pat<(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
|
||||
MOVLP_shuffle_mask)),
|
||||
(MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v4i32 (movhp VR128:$src1, (load addr:$src2))),
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
|
||||
MOVHP_shuffle_mask)),
|
||||
(MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
|
||||
def : Pat<(v2i64 (movhp VR128:$src1, (load addr:$src2))),
|
||||
def : Pat<(v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
|
||||
MOVHP_shuffle_mask)),
|
||||
(MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
||||
}
|
||||
|
||||
// (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
|
||||
// (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
|
||||
def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
|
||||
def : Pat<(store (v4f32 (vector_shuffle (load addr:$src1), VR128:$src2,
|
||||
MOVLP_shuffle_mask)), addr:$src1),
|
||||
(MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
|
||||
def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
|
||||
def : Pat<(store (v2f64 (vector_shuffle (load addr:$src1), VR128:$src2,
|
||||
MOVLP_shuffle_mask)), addr:$src1),
|
||||
(MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(store (v4f32 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
|
||||
def : Pat<(store (v4f32 (vector_shuffle (load addr:$src1), VR128:$src2,
|
||||
MOVHP_shuffle_mask)), addr:$src1),
|
||||
(MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
|
||||
def : Pat<(store (v2f64 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
|
||||
def : Pat<(store (v2f64 (vector_shuffle (load addr:$src1), VR128:$src2,
|
||||
MOVHP_shuffle_mask)), addr:$src1),
|
||||
(MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
||||
|
||||
def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
|
||||
addr:$src1),
|
||||
def : Pat<(store (v4i32 (vector_shuffle
|
||||
(bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2,
|
||||
MOVLP_shuffle_mask)), addr:$src1),
|
||||
(MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
|
||||
def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
|
||||
def : Pat<(store (v2i64 (vector_shuffle (load addr:$src1), VR128:$src2,
|
||||
MOVLP_shuffle_mask)), addr:$src1),
|
||||
(MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(store (v4i32 (movhp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
|
||||
addr:$src1),
|
||||
def : Pat<(store (v4i32 (vector_shuffle
|
||||
(bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2,
|
||||
MOVHP_shuffle_mask)), addr:$src1),
|
||||
(MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
|
||||
def : Pat<(store (v2i64 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
|
||||
def : Pat<(store (v2i64 (vector_shuffle (load addr:$src1), VR128:$src2,
|
||||
MOVHP_shuffle_mask)), addr:$src1),
|
||||
(MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
||||
|
||||
|
||||
let AddedComplexity = 15 in {
|
||||
// Setting the lowest element in the vector.
|
||||
def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
MOVL_shuffle_mask)),
|
||||
(MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
|
||||
def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
MOVL_shuffle_mask)),
|
||||
(MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
||||
|
||||
// vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
|
||||
def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
|
||||
def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
MOVLP_shuffle_mask)),
|
||||
(MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
|
||||
def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
|
||||
MOVLP_shuffle_mask)),
|
||||
(MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
||||
}
|
||||
|
||||
// Set lowest element and zero upper elements.
|
||||
let AddedComplexity = 15 in
|
||||
def : Pat<(v2f64 (movl immAllZerosV_bc, VR128:$src)),
|
||||
def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
|
||||
MOVL_shuffle_mask)),
|
||||
(MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
|
||||
def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
|
||||
(MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
|
||||
|
@ -1,7 +1,5 @@
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -o %t -f
|
||||
; RUN: not grep and %t
|
||||
; RUN: not grep psrldq %t
|
||||
; RUN: grep xorps %t
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin | not grep and
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin | grep psrldq
|
||||
|
||||
define <4 x float> @test(<4 x float>* %v1) nounwind {
|
||||
%tmp = load <4 x float>* %v1 ; <<4 x float>> [#uses=1]
|
||||
|
@ -1,7 +1,9 @@
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t -f
|
||||
; RUN: grep unpcklps %t | count 1
|
||||
; RUN: grep pshufd %t | count 1
|
||||
; RUN: not grep {sub.*esp} %t
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | \
|
||||
; RUN: grep unpcklps | count 1
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | \
|
||||
; RUN: grep unpckhps | count 1
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | \
|
||||
; RUN: not grep {sub.*esp}
|
||||
|
||||
define void @test(<4 x float>* %res, <4 x float>* %A, <4 x float>* %B) {
|
||||
%tmp = load <4 x float>* %B ; <<4 x float>> [#uses=2]
|
||||
|
@ -1,10 +1,8 @@
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,-sse2 -mtriple=i386-apple-darwin -o %t -f
|
||||
; RUN: grep shufps %t | count 4
|
||||
; RUN: grep movaps %t | count 2
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -o %t -f
|
||||
; RUN: grep pshufd %t | count 4
|
||||
; RUN: not grep shufps %t
|
||||
; RUN: not grep mov %t
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,-sse2 | grep shufps | count 4
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,-sse2 -mtriple=i386-apple-darwin | grep mov | count 2
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep pshufd | count 4
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep shufps
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin | not grep mov
|
||||
|
||||
define <4 x float> @t1(<4 x float> %a, <4 x float> %b) nounwind {
|
||||
%tmp1 = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer
|
||||
|
@ -1,7 +1,8 @@
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 -disable-mmx -o %t -f
|
||||
; RUN: grep pshufhw %t | grep 161 | count 1
|
||||
; RUN: grep shufps %t | count 1
|
||||
; RUN: not grep pslldq %t
|
||||
; RUN: grep pslldq %t | count 1
|
||||
|
||||
|
||||
|
||||
; Test case when creating pshufhw, we incorrectly set the higher order bit
|
||||
; for an undef,
|
||||
@ -19,4 +20,4 @@ entry:
|
||||
%0 = shufflevector <4 x i32> %in, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> < i32 undef, i32 5, i32 undef, i32 2>
|
||||
store <4 x i32> %0, <4 x i32>* %dest
|
||||
ret void
|
||||
}
|
||||
}
|
@ -1,6 +1,6 @@
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah -o %t -f
|
||||
; RUN: grep pextrw %t | count 1
|
||||
; RUN: grep movlhps %t | count 1
|
||||
; RUN: grep punpcklqdq %t | count 1
|
||||
; RUN: grep pshufhw %t | count 1
|
||||
; RUN: grep pinsrw %t | count 1
|
||||
; RUN: llvm-as < %s | llc -march=x86 -mcpu=core2 -o %t -f
|
||||
|
@ -194,6 +194,10 @@ SDTypeConstraint::SDTypeConstraint(Record *R) {
|
||||
ConstraintType = SDTCisOpSmallerThanOp;
|
||||
x.SDTCisOpSmallerThanOp_Info.BigOperandNum =
|
||||
R->getValueAsInt("BigOperandNum");
|
||||
} else if (R->isSubClassOf("SDTCisIntVectorOfSameSize")) {
|
||||
ConstraintType = SDTCisIntVectorOfSameSize;
|
||||
x.SDTCisIntVectorOfSameSize_Info.OtherOperandNum =
|
||||
R->getValueAsInt("OtherOpNum");
|
||||
} else if (R->isSubClassOf("SDTCisEltOfVec")) {
|
||||
ConstraintType = SDTCisEltOfVec;
|
||||
x.SDTCisEltOfVec_Info.OtherOperandNum =
|
||||
@ -361,9 +365,23 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,
|
||||
}
|
||||
return MadeChange;
|
||||
}
|
||||
case SDTCisIntVectorOfSameSize: {
|
||||
TreePatternNode *OtherOperand =
|
||||
getOperandNum(x.SDTCisIntVectorOfSameSize_Info.OtherOperandNum,
|
||||
N, NumResults);
|
||||
if (OtherOperand->hasTypeSet()) {
|
||||
if (!isVector(OtherOperand->getTypeNum(0)))
|
||||
TP.error(N->getOperator()->getName() + " VT operand must be a vector!");
|
||||
MVT IVT = OtherOperand->getTypeNum(0);
|
||||
unsigned NumElements = IVT.getVectorNumElements();
|
||||
IVT = MVT::getIntVectorWithNumElements(NumElements);
|
||||
return NodeToApply->UpdateNodeType(IVT.getSimpleVT(), TP);
|
||||
}
|
||||
return false;
|
||||
}
|
||||
case SDTCisEltOfVec: {
|
||||
TreePatternNode *OtherOperand =
|
||||
getOperandNum(x.SDTCisEltOfVec_Info.OtherOperandNum,
|
||||
getOperandNum(x.SDTCisIntVectorOfSameSize_Info.OtherOperandNum,
|
||||
N, NumResults);
|
||||
if (OtherOperand->hasTypeSet()) {
|
||||
if (!isVector(OtherOperand->getTypeNum(0)))
|
||||
@ -907,6 +925,25 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
|
||||
if (NI.getNumResults() == 0)
|
||||
MadeChange |= UpdateNodeType(MVT::isVoid, TP);
|
||||
|
||||
// If this is a vector_shuffle operation, apply types to the build_vector
|
||||
// operation. The types of the integers don't matter, but this ensures they
|
||||
// won't get checked.
|
||||
if (getOperator()->getName() == "vector_shuffle" &&
|
||||
getChild(2)->getOperator()->getName() == "build_vector") {
|
||||
TreePatternNode *BV = getChild(2);
|
||||
const std::vector<MVT::SimpleValueType> &LegalVTs
|
||||
= CDP.getTargetInfo().getLegalValueTypes();
|
||||
MVT::SimpleValueType LegalIntVT = MVT::Other;
|
||||
for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
|
||||
if (isInteger(LegalVTs[i]) && !isVector(LegalVTs[i])) {
|
||||
LegalIntVT = LegalVTs[i];
|
||||
break;
|
||||
}
|
||||
assert(LegalIntVT != MVT::Other && "No legal integer VT?");
|
||||
|
||||
for (unsigned i = 0, e = BV->getNumChildren(); i != e; ++i)
|
||||
MadeChange |= BV->getChild(i)->UpdateNodeType(LegalIntVT, TP);
|
||||
}
|
||||
return MadeChange;
|
||||
} else if (getOperator()->isSubClassOf("Instruction")) {
|
||||
const DAGInstruction &Inst = CDP.getInstruction(getOperator());
|
||||
@ -2049,9 +2086,6 @@ void CodeGenDAGPatterns::ParsePatterns() {
|
||||
IterateInference |= Result->getTree(0)->
|
||||
UpdateNodeType(Pattern->getTree(0)->getExtTypes(), *Result);
|
||||
} while (IterateInference);
|
||||
|
||||
// Blah?
|
||||
Result->getTree(0)->setTransformFn(Pattern->getTree(0)->getTransformFn());
|
||||
|
||||
// Verify that we inferred enough types that we can do something with the
|
||||
// pattern and result. If these fire the user has to add type casts.
|
||||
|
@ -62,7 +62,8 @@ struct SDTypeConstraint {
|
||||
unsigned OperandNo; // The operand # this constraint applies to.
|
||||
enum {
|
||||
SDTCisVT, SDTCisPtrTy, SDTCisInt, SDTCisFP, SDTCisSameAs,
|
||||
SDTCisVTSmallerThanOp, SDTCisOpSmallerThanOp, SDTCisEltOfVec
|
||||
SDTCisVTSmallerThanOp, SDTCisOpSmallerThanOp, SDTCisIntVectorOfSameSize,
|
||||
SDTCisEltOfVec
|
||||
} ConstraintType;
|
||||
|
||||
union { // The discriminated union.
|
||||
@ -78,6 +79,9 @@ struct SDTypeConstraint {
|
||||
struct {
|
||||
unsigned BigOperandNum;
|
||||
} SDTCisOpSmallerThanOp_Info;
|
||||
struct {
|
||||
unsigned OtherOperandNum;
|
||||
} SDTCisIntVectorOfSameSize_Info;
|
||||
struct {
|
||||
unsigned OtherOperandNum;
|
||||
} SDTCisEltOfVec_Info;
|
||||
|
Loading…
Reference in New Issue
Block a user