From 15715fb689a5c7a2476c943a7b06616bd6d67d5e Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Wed, 31 Jul 2013 12:38:08 +0000 Subject: [PATCH] [SystemZ] Be more careful about inverting CC masks (conditional loads) Extend r187495 to conditional loads. I split this out because the easiest way seemed to be to force a particular operand order in SystemZISelDAGToDAG.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187496 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 21 +++++++++++++++++++++ lib/Target/SystemZ/SystemZInstrFormats.td | 12 ++++++++---- lib/Target/SystemZ/SystemZInstrInfo.td | 6 ++---- lib/Target/SystemZ/SystemZOperands.td | 9 --------- lib/Target/SystemZ/SystemZPatterns.td | 14 -------------- test/CodeGen/SystemZ/cond-load-01.ll | 14 +++++++------- test/CodeGen/SystemZ/cond-load-02.ll | 14 +++++++------- 7 files changed, 45 insertions(+), 45 deletions(-) diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index b7e966ff011..d9794b1d643 100644 --- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -1012,6 +1012,27 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) { } } break; + + case SystemZISD::SELECT_CCMASK: { + SDValue Op0 = Node->getOperand(0); + SDValue Op1 = Node->getOperand(1); + // Prefer to put any load first, so that it can be matched as a + // conditional load. + if (Op1.getOpcode() == ISD::LOAD && Op0.getOpcode() != ISD::LOAD) { + SDValue CCValid = Node->getOperand(2); + SDValue CCMask = Node->getOperand(3); + uint64_t ConstCCValid = + cast(CCValid.getNode())->getZExtValue(); + uint64_t ConstCCMask = + cast(CCMask.getNode())->getZExtValue(); + // Invert the condition. + CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask, + CCMask.getValueType()); + SDValue Op4 = Node->getOperand(4); + Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4); + } + break; + } } // Select the default instruction diff --git a/lib/Target/SystemZ/SystemZInstrFormats.td b/lib/Target/SystemZ/SystemZInstrFormats.td index c0bb7b73c76..915891d09d7 100644 --- a/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/lib/Target/SystemZ/SystemZInstrFormats.td @@ -735,10 +735,14 @@ class UnaryRILPC opcode, SDPatternOperator operator, } class CondUnaryRSY opcode, - RegisterOperand cls, bits<5> bytes, - AddressingMode mode = bdaddr20only> - : InstRSY, + SDPatternOperator operator, RegisterOperand cls, + bits<5> bytes, AddressingMode mode = bdaddr20only> + : InstRSY, Requires<[FeatureLoadStoreOnCond]> { let Constraints = "$R1 = $R1src"; let DisableEncoding = "$R1src"; diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index a6efd41d043..341eb904040 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -272,15 +272,13 @@ let canFoldAsLoad = 1 in { // Load on condition. let isCodeGenOnly = 1, Uses = [CC] in { - def LOC : CondUnaryRSY<"loc", 0xEBF2, GR32, 4>; - def LOCG : CondUnaryRSY<"locg", 0xEBE2, GR64, 8>; + def LOC : CondUnaryRSY<"loc", 0xEBF2, nonvolatile_load, GR32, 4>; + def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>; } let Uses = [CC] in { def AsmLOC : AsmCondUnaryRSY<"loc", 0xEBF2, GR32, 4>; def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>; } -defm : CondLoad; -defm : CondLoad; // Register stores. let SimpleBDXStore = 1 in { diff --git a/lib/Target/SystemZ/SystemZOperands.td b/lib/Target/SystemZ/SystemZOperands.td index 696ec4f15a1..9d794392280 100644 --- a/lib/Target/SystemZ/SystemZOperands.td +++ b/lib/Target/SystemZ/SystemZOperands.td @@ -110,15 +110,6 @@ class BDLMode("disp"##dispsize##"imm"##bitsize), !cast("imm"##bitsize))>; -//===----------------------------------------------------------------------===// -// Manipulating CC masks -//===----------------------------------------------------------------------===// - -def INVCC : SDNodeXFormgetZExtValue() ^ SystemZ::CCMASK_ANY; - return CurDAG->getTargetConstant(Value, MVT::i8); -}]>; - //===----------------------------------------------------------------------===// // Extracting immediate operands from nodes // These all create MVT::i64 nodes to ensure the value is not sign-extended diff --git a/lib/Target/SystemZ/SystemZPatterns.td b/lib/Target/SystemZ/SystemZPatterns.td index 5419c2badf9..74cc5f019a8 100644 --- a/lib/Target/SystemZ/SystemZPatterns.td +++ b/lib/Target/SystemZ/SystemZPatterns.td @@ -54,20 +54,6 @@ multiclass RMWIByte; } -// Record that INSN conditionally performs load operation LOAD into a -// register of class CLS. The load may trap even if the condition is false. -multiclass CondLoad { - def : Pat<(z_select_ccmask (load bdaddr20only:$addr), cls:$new, uimm8zx4, - uimm8zx4:$cc), - (insn cls:$new, bdaddr20only:$addr, uimm8zx4:$cc)>, - Requires<[FeatureLoadStoreOnCond]>; - def : Pat<(z_select_ccmask cls:$new, (load bdaddr20only:$addr), uimm8zx4, - uimm8zx4:$cc), - (insn cls:$new, bdaddr20only:$addr, (INVCC uimm8zx4:$cc))>, - Requires<[FeatureLoadStoreOnCond]>; -} - // Record that INSN performs insertion TYPE into a register of class CLS. // The inserted operand is loaded using LOAD from an address of mode MODE. multiclass InsertMem