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Fix SRS/SRSW encoding bits.

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rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS

Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128864 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-05 00:16:18 +00:00
parent 597028cc28
commit 157536b1fb
3 changed files with 28 additions and 0 deletions
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4
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1589,6 +1589,8 @@ def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
[/* For disassembly only; pattern left blank */]> { [/* For disassembly only; pattern left blank */]> {
let Inst{31-28} = 0b1111; let Inst{31-28} = 0b1111;
let Inst{22-20} = 0b110; // W = 1 let Inst{22-20} = 0b110; // W = 1
let Inst{19-8} = 0xd05;
let Inst{7-5} = 0b000;
} }
def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode), def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
@ -1596,6 +1598,8 @@ def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
[/* For disassembly only; pattern left blank */]> { [/* For disassembly only; pattern left blank */]> {
let Inst{31-28} = 0b1111; let Inst{31-28} = 0b1111;
let Inst{22-20} = 0b100; // W = 0 let Inst{22-20} = 0b100; // W = 0
let Inst{19-8} = 0xd05;
let Inst{7-5} = 0b000;
} }
// Return From Exception is a system instruction -- for disassembly only // Return From Exception is a system instruction -- for disassembly only

11
test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt Normal file
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@ -0,0 +1,11 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0|
# -------------------------------------------------------------------------------------------------
#
# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction
# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction
0x32 0xb1 0x99 0xf8

13
test/MC/Disassembler/ARM/invalid-SRS-arm.txt Normal file
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@ -0,0 +1,13 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=0 Name=PHI Format=(42)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1|
# -------------------------------------------------------------------------------------------------
# Unknown format
#
# B6.1.10 SRS
# Inst{19-8} = 0xd05
# Inst{7-5} = 0b000
0x83 0x1c 0xc5 0xf8