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More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -109,7 +109,7 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
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const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
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const TargetRegisterClass *RC = 0;
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if (i+II.getNumDefs() < II.getNumOperands())
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RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI);
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RC = TII->getRegClass(II, i+II.getNumDefs(), TRI);
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if (!UseRC)
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UseRC = RC;
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else if (RC) {
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@@ -189,7 +189,7 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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// is a vreg in the same register class, use the CopyToReg'd destination
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// register instead of creating a new vreg.
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unsigned VRBase = 0;
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const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI);
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const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI);
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if (II.OpInfo[i].isOptionalDef()) {
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// Optional def must be a physical register.
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unsigned NumResults = CountResults(Node);
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@@ -285,7 +285,7 @@ InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
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const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
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const TargetRegisterClass *DstRC = 0;
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if (IIOpNum < II->getNumOperands())
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DstRC = II->OpInfo[IIOpNum].getRegClass(TRI);
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DstRC = TII->getRegClass(*II, IIOpNum, TRI);
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assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
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"Don't have operand info for this instruction!");
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if (DstRC && !SrcRC->hasSuperClassEq(DstRC)) {
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@@ -303,7 +303,7 @@ static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
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unsigned Idx = RegDefPos.GetIdx();
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const TargetInstrDesc Desc = TII->get(Opcode);
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const TargetRegisterClass *RC = Desc.getRegClass(Idx, TRI);
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const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI);
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RegClass = RC->getID();
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// FIXME: Cost arbitrarily set to 1 because there doesn't seem to be a
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// better way to determine it.
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