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More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2011-06-27 21:26:13 +00:00
parent bea6f615ee
commit 15993f83a4
18 changed files with 54 additions and 63 deletions
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2
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -1673,7 +1673,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
Ops.pop_back();
const TargetInstrDesc &TID = TII->get(NewOpc);
const TargetRegisterClass *TRC = TID.OpInfo[0].getRegClass(TRI);
const TargetRegisterClass *TRC = TII->getRegClass(TID, 0, TRI);
MRI->constrainRegClass(EvenReg, TRC);
MRI->constrainRegClass(OddReg, TRC);