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https://github.com/c64scene-ar/llvm-6502.git
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More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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bea6f615ee
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@ -52,9 +52,6 @@ public:
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/// if the operand is a register. If isLookupPtrRegClass is set, then this is
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/// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to
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/// get a dynamic register class.
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///
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/// NOTE: This member should be considered to be private, all access should go
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/// through "getRegClass(TRI)" below.
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short RegClass;
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/// Flags - These are flags from the TOI::OperandFlags enum.
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@ -65,12 +62,6 @@ public:
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unsigned Constraints;
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/// Currently no other information.
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/// getRegClass - Get the register class for the operand, handling resolution
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/// of "symbolic" pointer register classes etc. If this is not a register
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/// operand, this returns null.
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const TargetRegisterClass *getRegClass(const TargetRegisterInfo *TRI) const;
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/// isLookupPtrRegClass - Set if this operand is a pointer value and it
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/// requires a callback to look up its register class.
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bool isLookupPtrRegClass() const { return Flags&(1 <<TOI::LookupPtrRegClass);}
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@ -154,12 +145,6 @@ public:
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return -1;
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}
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/// getRegClass - Returns the register class constraint for OpNum, or NULL.
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const TargetRegisterClass *getRegClass(unsigned OpNum,
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const TargetRegisterInfo *TRI) const {
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return OpNum < NumOperands ? OpInfo[OpNum].getRegClass(TRI) : 0;
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}
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/// getOpcode - Return the opcode number for this descriptor.
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unsigned getOpcode() const {
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return Opcode;
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@ -60,6 +60,12 @@ public:
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return Descriptors[Opcode];
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}
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/// getRegClass - Givem a machine instruction descriptor, returns the register
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/// class constraint for OpNum, or NULL.
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const TargetRegisterClass *getRegClass(const TargetInstrDesc &TID,
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unsigned OpNum,
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const TargetRegisterInfo *TRI) const;
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/// isTriviallyReMaterializable - Return true if the instruction is trivially
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/// rematerializable, meaning it has no side effects and requires no operands
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/// that aren't always available.
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@ -404,7 +404,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI,
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// Note register reference...
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const TargetRegisterClass *RC = NULL;
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if (i < MI->getDesc().getNumOperands())
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RC = MI->getDesc().OpInfo[i].getRegClass(TRI);
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RC = TII->getRegClass(MI->getDesc(), i, TRI);
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AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
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RegRefs.insert(std::make_pair(Reg, RR));
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}
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@ -479,7 +479,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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// Note register reference...
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const TargetRegisterClass *RC = NULL;
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if (i < MI->getDesc().getNumOperands())
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RC = MI->getDesc().OpInfo[i].getRegClass(TRI);
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RC = TII->getRegClass(MI->getDesc(), i, TRI);
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AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
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RegRefs.insert(std::make_pair(Reg, RR));
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}
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@ -188,6 +188,7 @@ void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
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void VirtRegAuxInfo::CalculateRegClass(unsigned reg) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
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const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
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const TargetRegisterClass *OldRC = MRI.getRegClass(reg);
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const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
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@ -203,7 +204,7 @@ void VirtRegAuxInfo::CalculateRegClass(unsigned reg) {
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if (I.getOperand().getSubReg())
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return;
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const TargetRegisterClass *OpRC =
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I->getDesc().getRegClass(I.getOperandNo(), TRI);
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TII->getRegClass(I->getDesc(), I.getOperandNo(), TRI);
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if (OpRC)
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NewRC = getCommonSubClass(NewRC, OpRC);
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if (!NewRC || NewRC == OldRC)
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@ -207,7 +207,7 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
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const TargetRegisterClass *NewRC = 0;
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if (i < MI->getDesc().getNumOperands())
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NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
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NewRC = TII->getRegClass(MI->getDesc(), i, TRI);
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// For now, only allow the register to be changed if its register
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// class is consistent across all uses.
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@ -295,7 +295,7 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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const TargetRegisterClass *NewRC = 0;
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if (i < MI->getDesc().getNumOperands())
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NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI);
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NewRC = TII->getRegClass(MI->getDesc(), i, TRI);
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// For now, only allow the register to be changed if its register
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// class is consistent across all uses.
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@ -1020,7 +1020,7 @@ MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
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if (NewOpc == 0) return 0;
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const TargetInstrDesc &TID = TII->get(NewOpc);
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if (TID.getNumDefs() != 1) return 0;
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const TargetRegisterClass *RC = TID.OpInfo[LoadRegIndex].getRegClass(TRI);
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const TargetRegisterClass *RC = TII->getRegClass(TID, LoadRegIndex, TRI);
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// Ok, we're unfolding. Create a temporary register and do the unfold.
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unsigned Reg = MRI->createVirtualRegister(RC);
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@ -62,6 +62,7 @@ namespace {
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raw_ostream *OS;
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const MachineFunction *MF;
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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const MachineRegisterInfo *MRI;
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@ -255,6 +256,7 @@ bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
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this->MF = &MF;
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TM = &MF.getTarget();
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TII = TM->getInstrInfo();
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TRI = TM->getRegisterInfo();
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MRI = &MF.getRegInfo();
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@ -387,8 +389,6 @@ static bool matchPair(MachineBasicBlock::const_succ_iterator i,
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void
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MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
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const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
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// Count the number of landing pad successors.
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SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
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for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
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@ -723,7 +723,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
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}
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sr = s;
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}
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if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
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if (const TargetRegisterClass *DRC = TII->getRegClass(TI, MONum, TRI)) {
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if (!DRC->contains(sr)) {
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report("Illegal physical register for instruction", MO, MONum);
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*OS << TRI->getName(sr) << " is not a "
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@ -743,7 +743,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
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}
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RC = SRC;
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}
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if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) {
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if (const TargetRegisterClass *DRC = TII->getRegClass(TI, MONum, TRI)) {
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if (!RC->hasSuperClassEq(DRC)) {
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report("Illegal virtual register for instruction", MO, MONum);
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*OS << "Expected a " << DRC->getName() << " register, but got a "
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@ -701,7 +701,7 @@ bool RegisterCoalescer::ReMaterializeTrivialDef(LiveInterval &SrcInt,
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// Make sure the copy destination register class fits the instruction
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// definition register class. The mismatch can happen as a result of earlier
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// extract_subreg, insert_subreg, subreg_to_reg coalescing.
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const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_);
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const TargetRegisterClass *RC = tii_->getRegClass(TID, 0, tri_);
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if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
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if (mri_->getRegClass(DstReg) != RC)
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return false;
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@ -718,7 +718,7 @@ bool RegisterCoalescer::ReMaterializeTrivialDef(LiveInterval &SrcInt,
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const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
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const TargetRegisterClass *DstSubRC =
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DstRC->getSubRegisterRegClass(DstSubIdx);
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const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
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const TargetRegisterClass *DefRC = tii_->getRegClass(TID, 0, tri_);
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if (DefRC == DstRC)
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DstSubIdx = 0;
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else if (DefRC != DstSubRC)
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@ -109,7 +109,7 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
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const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
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const TargetRegisterClass *RC = 0;
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if (i+II.getNumDefs() < II.getNumOperands())
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RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI);
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RC = TII->getRegClass(II, i+II.getNumDefs(), TRI);
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if (!UseRC)
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UseRC = RC;
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else if (RC) {
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@ -189,7 +189,7 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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// is a vreg in the same register class, use the CopyToReg'd destination
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// register instead of creating a new vreg.
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unsigned VRBase = 0;
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const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI);
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const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI);
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if (II.OpInfo[i].isOptionalDef()) {
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// Optional def must be a physical register.
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unsigned NumResults = CountResults(Node);
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@ -285,7 +285,7 @@ InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
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const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
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const TargetRegisterClass *DstRC = 0;
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if (IIOpNum < II->getNumOperands())
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DstRC = II->OpInfo[IIOpNum].getRegClass(TRI);
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DstRC = TII->getRegClass(*II, IIOpNum, TRI);
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assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
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"Don't have operand info for this instruction!");
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if (DstRC && !SrcRC->hasSuperClassEq(DstRC)) {
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@ -303,7 +303,7 @@ static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
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unsigned Idx = RegDefPos.GetIdx();
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const TargetInstrDesc Desc = TII->get(Opcode);
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const TargetRegisterClass *RC = Desc.getRegClass(Idx, TRI);
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const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI);
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RegClass = RC->getID();
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// FIXME: Cost arbitrarily set to 1 because there doesn't seem to be a
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// better way to determine it.
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@ -521,7 +521,7 @@ bool StackSlotColoring::PropagateBackward(MachineBasicBlock::iterator MII,
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if (MO.getSubReg() || MII->isSubregToReg())
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return false;
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const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
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const TargetRegisterClass *RC = TII->getRegClass(TID, i, TRI);
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if (RC && !RC->contains(NewReg))
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return false;
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@ -583,7 +583,7 @@ bool StackSlotColoring::PropagateForward(MachineBasicBlock::iterator MII,
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if (MO.getSubReg())
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return false;
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const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
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const TargetRegisterClass *RC = TII->getRegClass(TID, i, TRI);
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if (RC && !RC->contains(NewReg))
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return false;
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if (MO.isKill())
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// Unfold the load.
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DEBUG(dbgs() << "2addr: UNFOLDING: " << *mi);
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const TargetRegisterClass *RC =
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UnfoldTID.OpInfo[LoadRegIndex].getRegClass(TRI);
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TII->getRegClass(UnfoldTID, LoadRegIndex, TRI);
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unsigned Reg = MRI->createVirtualRegister(RC);
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SmallVector<MachineInstr *, 2> NewMIs;
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if (!TII->unfoldMemoryOperand(MF, mi, Reg,
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@ -1112,7 +1112,7 @@ materializeFrameBaseRegister(MachineBasicBlock *MBB,
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const TargetInstrDesc &TID = TII.get(ADDriOpc);
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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MRI.constrainRegClass(BaseReg, TID.OpInfo[0].getRegClass(this));
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MRI.constrainRegClass(BaseReg, TII.getRegClass(TID, 0, this));
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MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, TID, BaseReg)
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.addFrameIndex(FrameIdx).addImm(Offset);
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@ -1673,7 +1673,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
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Ops.pop_back();
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const TargetInstrDesc &TID = TII->get(NewOpc);
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const TargetRegisterClass *TRC = TID.OpInfo[0].getRegClass(TRI);
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const TargetRegisterClass *TRC = TII->getRegClass(TID, 0, TRI);
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MRI->constrainRegClass(EvenReg, TRC);
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MRI->constrainRegClass(OddReg, TRC);
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@ -220,7 +220,7 @@ MLxExpansion::ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI,
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const TargetInstrDesc &TID1 = TII->get(MulOpc);
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const TargetInstrDesc &TID2 = TII->get(AddSubOpc);
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unsigned TmpReg = MRI->createVirtualRegister(TID1.getRegClass(0, TRI));
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unsigned TmpReg = MRI->createVirtualRegister(TII->getRegClass(TID1, 0, TRI));
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MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), TID1, TmpReg)
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.addReg(Src1Reg, getKillRegState(Src1Kill))
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@ -154,13 +154,13 @@ void BlackfinDAGToDAGISel::FixRegisterClasses(SelectionDAG &DAG) {
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if (UI.getUse().getResNo() >= DefTID.getNumDefs())
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continue;
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const TargetRegisterClass *DefRC =
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DefTID.OpInfo[UI.getUse().getResNo()].getRegClass(TRI);
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TII.getRegClass(DefTID, UI.getUse().getResNo(), TRI);
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const TargetInstrDesc &UseTID = TII.get(UI->getMachineOpcode());
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if (UseTID.getNumDefs()+UI.getOperandNo() >= UseTID.getNumOperands())
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continue;
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const TargetRegisterClass *UseRC =
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UseTID.OpInfo[UseTID.getNumDefs()+UI.getOperandNo()].getRegClass(TRI);
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TII.getRegClass(UseTID, UseTID.getNumDefs()+UI.getOperandNo(), TRI);
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if (!DefRC || !UseRC)
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continue;
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// We cannot copy CC <-> !(CC/D)
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@ -20,24 +20,6 @@
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#include <cctype>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// TargetOperandInfo
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//===----------------------------------------------------------------------===//
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/// getRegClass - Get the register class for the operand, handling resolution
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/// of "symbolic" pointer register classes etc. If this is not a register
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/// operand, this returns null.
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const TargetRegisterClass *
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TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const {
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if (isLookupPtrRegClass())
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return TRI->getPointerRegClass(RegClass);
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// Instructions like INSERT_SUBREG do not have fixed register classes.
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if (RegClass < 0)
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return 0;
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// Otherwise just look it up normally.
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return TRI->getRegClass(RegClass);
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}
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//===----------------------------------------------------------------------===//
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// TargetInstrInfo
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//===----------------------------------------------------------------------===//
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@ -50,6 +32,24 @@ TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
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TargetInstrInfo::~TargetInstrInfo() {
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}
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const TargetRegisterClass*
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TargetInstrInfo::getRegClass(const TargetInstrDesc &TID, unsigned OpNum,
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const TargetRegisterInfo *TRI) const {
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if (OpNum >= TID.getNumOperands())
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return 0;
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short RegClass = TID.OpInfo[OpNum].RegClass;
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if (TID.OpInfo[OpNum].isLookupPtrRegClass())
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return TRI->getPointerRegClass(RegClass);
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// Instructions like INSERT_SUBREG do not have fixed register classes.
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if (RegClass < 0)
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return 0;
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// Otherwise just look it up normally.
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return TRI->getRegClass(RegClass);
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}
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unsigned
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TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
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const MachineInstr *MI) const {
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@ -2274,7 +2274,7 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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return NULL;
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bool NarrowToMOV32rm = false;
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if (Size) {
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unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
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unsigned RCSize = getRegClass(MI->getDesc(), i, &RI)->getSize();
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if (Size < RCSize) {
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// Check if it's safe to fold the load. If the size of the object is
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// narrower than the load width, then it's not.
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@ -2590,8 +2590,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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UnfoldStore &= FoldedStore;
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const TargetInstrDesc &TID = get(Opc);
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const TargetOperandInfo &TOI = TID.OpInfo[Index];
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const TargetRegisterClass *RC = TOI.getRegClass(&RI);
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const TargetRegisterClass *RC = getRegClass(TID, Index, &RI);
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if (!MI->hasOneMemOperand() &&
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RC == &X86::VR128RegClass &&
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!TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
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@ -2686,7 +2685,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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// Emit the store instruction.
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if (UnfoldStore) {
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const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
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const TargetRegisterClass *DstRC = getRegClass(TID, 0, &RI);
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std::pair<MachineInstr::mmo_iterator,
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MachineInstr::mmo_iterator> MMOs =
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MF.extractStoreMemRefs(MI->memoperands_begin(),
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@ -2712,7 +2711,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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bool FoldedLoad = I->second.second & (1 << 4);
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bool FoldedStore = I->second.second & (1 << 5);
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const TargetInstrDesc &TID = get(Opc);
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const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
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const TargetRegisterClass *RC = getRegClass(TID, Index, &RI);
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unsigned NumDefs = TID.NumDefs;
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std::vector<SDValue> AddrOps;
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std::vector<SDValue> BeforeOps;
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@ -2758,7 +2757,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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std::vector<EVT> VTs;
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const TargetRegisterClass *DstRC = 0;
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if (TID.getNumDefs() > 0) {
|
||||
DstRC = TID.OpInfo[0].getRegClass(&RI);
|
||||
DstRC = getRegClass(TID, 0, &RI);
|
||||
VTs.push_back(*DstRC->vt_begin());
|
||||
}
|
||||
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
|
||||
|
Loading…
Reference in New Issue
Block a user