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Merging r213915:
------------------------------------------------------------------------ r213915 | wschmidt | 2014-07-24 18:55:55 -0700 (Thu, 24 Jul 2014) | 21 lines [PATCH][PPC64LE] Correct little-endian usage of vmrgh* and vmrgl*. Because the PowerPC vmrgh* and vmrgl* instructions have a built-in big-endian bias, it is necessary to swap their inputs in little-endian mode when using them to implement a vector shuffle. This was previously missed in the vector LE implementation. There was already logic to distinguish between unary and "normal" vmrg* vector shuffles, so this patch extends that logic to use a third option: "swapped" vmrg* vector shuffles that are used for little endian in place of the "normal" ones. I've updated the vec-shuffle-le.ll test to check for the expected register ordering on the generated instructions. This bug was discovered when testing the LE and ELFv2 patches for safety if they were backported to 3.4. A different vectorization decision was made in 3.4 than on mainline trunk, and that exposed the problem. I've verified this fix takes care of that issue. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@213961 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
b3a02edc53
commit
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@ -32,12 +32,12 @@ dnl===-----------------------------------------------------------------------===
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dnl Initialize autoconf and define the package name, version number and
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dnl address for reporting bugs.
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AC_INIT([LLVM],[3.5.0svn],[http://llvm.org/bugs/])
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AC_INIT([LLVM],[3.5.0],[http://llvm.org/bugs/])
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LLVM_VERSION_MAJOR=3
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LLVM_VERSION_MINOR=5
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LLVM_VERSION_PATCH=0
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LLVM_VERSION_SUFFIX=svn
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LLVM_VERSION_SUFFIX=
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AC_DEFINE_UNQUOTED([LLVM_VERSION_MAJOR], $LLVM_VERSION_MAJOR, [Major version of the LLVM API])
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AC_DEFINE_UNQUOTED([LLVM_VERSION_MINOR], $LLVM_VERSION_MINOR, [Minor version of the LLVM API])
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20
configure
vendored
20
configure
vendored
@ -1,6 +1,6 @@
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#! /bin/sh
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# Guess values for system-dependent variables and create Makefiles.
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# Generated by GNU Autoconf 2.60 for LLVM 3.5.0svn.
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# Generated by GNU Autoconf 2.60 for LLVM 3.5.0.
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#
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# Report bugs to <http://llvm.org/bugs/>.
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#
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@ -561,8 +561,8 @@ SHELL=${CONFIG_SHELL-/bin/sh}
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# Identity of this package.
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PACKAGE_NAME='LLVM'
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PACKAGE_TARNAME='llvm'
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PACKAGE_VERSION='3.5.0svn'
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PACKAGE_STRING='LLVM 3.5.0svn'
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PACKAGE_VERSION='3.5.0'
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PACKAGE_STRING='LLVM 3.5.0'
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PACKAGE_BUGREPORT='http://llvm.org/bugs/'
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ac_unique_file="lib/IR/Module.cpp"
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@ -1326,7 +1326,7 @@ if test "$ac_init_help" = "long"; then
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# Omit some internal or obsolete options to make the list less imposing.
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# This message is too long to be a string in the A/UX 3.1 sh.
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cat <<_ACEOF
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\`configure' configures LLVM 3.5.0svn to adapt to many kinds of systems.
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\`configure' configures LLVM 3.5.0 to adapt to many kinds of systems.
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Usage: $0 [OPTION]... [VAR=VALUE]...
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@ -1392,7 +1392,7 @@ fi
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if test -n "$ac_init_help"; then
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case $ac_init_help in
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short | recursive ) echo "Configuration of LLVM 3.5.0svn:";;
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short | recursive ) echo "Configuration of LLVM 3.5.0:";;
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esac
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cat <<\_ACEOF
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@ -1565,7 +1565,7 @@ fi
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test -n "$ac_init_help" && exit $ac_status
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if $ac_init_version; then
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cat <<\_ACEOF
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LLVM configure 3.5.0svn
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LLVM configure 3.5.0
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generated by GNU Autoconf 2.60
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Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
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@ -1581,7 +1581,7 @@ cat >config.log <<_ACEOF
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This file contains any messages produced by compilers while
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running configure, to aid debugging if configure makes a mistake.
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It was created by LLVM $as_me 3.5.0svn, which was
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It was created by LLVM $as_me 3.5.0, which was
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generated by GNU Autoconf 2.60. Invocation command line was
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$ $0 $@
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@ -1938,7 +1938,7 @@ ac_compiler_gnu=$ac_cv_c_compiler_gnu
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LLVM_VERSION_MAJOR=3
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LLVM_VERSION_MINOR=5
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LLVM_VERSION_PATCH=0
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LLVM_VERSION_SUFFIX=svn
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LLVM_VERSION_SUFFIX=
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cat >>confdefs.h <<_ACEOF
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@ -19860,7 +19860,7 @@ exec 6>&1
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# report actual input values of CONFIG_FILES etc. instead of their
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# values after options handling.
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ac_log="
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This file was extended by LLVM $as_me 3.5.0svn, which was
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This file was extended by LLVM $as_me 3.5.0, which was
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generated by GNU Autoconf 2.60. Invocation command line was
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CONFIG_FILES = $CONFIG_FILES
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@ -19913,7 +19913,7 @@ Report bugs to <bug-autoconf@gnu.org>."
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_ACEOF
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cat >>$CONFIG_STATUS <<_ACEOF
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ac_cs_version="\\
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LLVM config.status 3.5.0svn
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LLVM config.status 3.5.0
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configured by $0, generated by GNU Autoconf 2.60,
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with options \\"`echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\"
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@ -5,11 +5,6 @@ LLVM 3.5 Release Notes
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.. contents::
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:local:
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.. warning::
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These are in-progress notes for the upcoming LLVM 3.5 release. You may
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prefer the `LLVM 3.4 Release Notes <http://llvm.org/releases/3.4/docs
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/ReleaseNotes.html>`_.
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Introduction
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============
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@ -919,31 +919,51 @@ static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
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/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
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/// The ShuffleKind distinguishes between big-endian merges with two
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/// different inputs (0), either-endian merges with two identical inputs (1),
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/// and little-endian merges with two different inputs (2). For the latter,
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/// the input operands are swapped (see PPCInstrAltivec.td).
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bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
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bool isUnary, SelectionDAG &DAG) {
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unsigned ShuffleKind, SelectionDAG &DAG) {
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if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
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if (!isUnary)
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if (ShuffleKind == 1) // unary
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return isVMerge(N, UnitSize, 0, 0);
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else if (ShuffleKind == 2) // swapped
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return isVMerge(N, UnitSize, 0, 16);
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return isVMerge(N, UnitSize, 0, 0);
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else
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return false;
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} else {
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if (!isUnary)
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if (ShuffleKind == 1) // unary
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return isVMerge(N, UnitSize, 8, 8);
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else if (ShuffleKind == 0) // normal
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return isVMerge(N, UnitSize, 8, 24);
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return isVMerge(N, UnitSize, 8, 8);
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else
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return false;
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}
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}
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/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
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/// The ShuffleKind distinguishes between big-endian merges with two
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/// different inputs (0), either-endian merges with two identical inputs (1),
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/// and little-endian merges with two different inputs (2). For the latter,
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/// the input operands are swapped (see PPCInstrAltivec.td).
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bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
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bool isUnary, SelectionDAG &DAG) {
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unsigned ShuffleKind, SelectionDAG &DAG) {
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if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
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if (!isUnary)
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if (ShuffleKind == 1) // unary
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return isVMerge(N, UnitSize, 8, 8);
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else if (ShuffleKind == 2) // swapped
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return isVMerge(N, UnitSize, 8, 24);
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return isVMerge(N, UnitSize, 8, 8);
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else
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return false;
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} else {
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if (!isUnary)
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if (ShuffleKind == 1) // unary
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return isVMerge(N, UnitSize, 0, 0);
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else if (ShuffleKind == 0) // normal
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return isVMerge(N, UnitSize, 0, 16);
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return isVMerge(N, UnitSize, 0, 0);
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else
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return false;
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}
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}
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@ -6014,12 +6034,12 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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PPC::isVPKUWUMShuffleMask(SVOp, true, DAG) ||
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PPC::isVPKUHUMShuffleMask(SVOp, true, DAG) ||
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PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
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PPC::isVMRGLShuffleMask(SVOp, 1, true, DAG) ||
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PPC::isVMRGLShuffleMask(SVOp, 2, true, DAG) ||
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PPC::isVMRGLShuffleMask(SVOp, 4, true, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 1, true, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 2, true, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 4, true, DAG)) {
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PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
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PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
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PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
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return Op;
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}
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}
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@ -6027,15 +6047,16 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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// Altivec has a variety of "shuffle immediates" that take two vector inputs
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// and produce a fixed permutation. If any of these match, do not lower to
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// VPERM.
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unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
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if (PPC::isVPKUWUMShuffleMask(SVOp, false, DAG) ||
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PPC::isVPKUHUMShuffleMask(SVOp, false, DAG) ||
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PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
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PPC::isVMRGLShuffleMask(SVOp, 1, false, DAG) ||
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PPC::isVMRGLShuffleMask(SVOp, 2, false, DAG) ||
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PPC::isVMRGLShuffleMask(SVOp, 4, false, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 1, false, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 2, false, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 4, false, DAG))
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PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
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PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
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PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
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PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
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return Op;
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// Check to see if this is a shuffle of 4-byte values. If so, we can use our
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@ -308,12 +308,12 @@ namespace llvm {
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/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
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bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
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bool isUnary, SelectionDAG &DAG);
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unsigned ShuffleKind, SelectionDAG &DAG);
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/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
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bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
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bool isUnary, SelectionDAG &DAG);
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unsigned ShuffleKind, SelectionDAG &DAG);
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/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
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/// amount, otherwise return -1.
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@ -44,65 +44,81 @@ def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
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return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false,
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*CurDAG);
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return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
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}]>;
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def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
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return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false,
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*CurDAG);
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return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
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}]>;
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def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
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return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false,
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*CurDAG);
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return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
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}]>;
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def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
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return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false,
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*CurDAG);
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return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 0, *CurDAG);
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}]>;
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def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
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return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false,
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*CurDAG);
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return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 0, *CurDAG);
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}]>;
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def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
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return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false,
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*CurDAG);
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return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 0, *CurDAG);
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}]>;
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def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
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return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true,
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*CurDAG);
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return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
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}]>;
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def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true,
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*CurDAG);
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return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
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}]>;
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def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true,
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*CurDAG);
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return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
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}]>;
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def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true,
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*CurDAG);
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return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 1, *CurDAG);
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}]>;
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def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true,
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*CurDAG);
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return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 1, *CurDAG);
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}]>;
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def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true,
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*CurDAG);
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return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 1, *CurDAG);
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}]>;
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// These fragments are provided for little-endian, where the inputs must be
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// swapped for correct semantics.
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def vmrglb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle (v16i8 node:$lhs), node:$rhs), [{
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return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
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}]>;
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def vmrglh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
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}]>;
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def vmrglw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
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}]>;
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def vmrghb_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, 2, *CurDAG);
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}]>;
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def vmrghh_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, 2, *CurDAG);
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}]>;
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def vmrghw_swapped_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, 2, *CurDAG);
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}]>;
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|
||||
@ -803,6 +819,22 @@ def:Pat<(vmrghh_unary_shuffle v16i8:$vA, undef),
|
||||
def:Pat<(vmrghw_unary_shuffle v16i8:$vA, undef),
|
||||
(VMRGHW $vA, $vA)>;
|
||||
|
||||
// Match vmrg*(y,x), i.e., swapped operands. These fragments
|
||||
// are matched for little-endian, where the inputs must be
|
||||
// swapped for correct semantics.
|
||||
def:Pat<(vmrglb_swapped_shuffle v16i8:$vA, v16i8:$vB),
|
||||
(VMRGLB $vB, $vA)>;
|
||||
def:Pat<(vmrglh_swapped_shuffle v16i8:$vA, v16i8:$vB),
|
||||
(VMRGLH $vB, $vA)>;
|
||||
def:Pat<(vmrglw_swapped_shuffle v16i8:$vA, v16i8:$vB),
|
||||
(VMRGLW $vB, $vA)>;
|
||||
def:Pat<(vmrghb_swapped_shuffle v16i8:$vA, v16i8:$vB),
|
||||
(VMRGHB $vB, $vA)>;
|
||||
def:Pat<(vmrghh_swapped_shuffle v16i8:$vA, v16i8:$vB),
|
||||
(VMRGHH $vB, $vA)>;
|
||||
def:Pat<(vmrghw_swapped_shuffle v16i8:$vA, v16i8:$vB),
|
||||
(VMRGHW $vB, $vA)>;
|
||||
|
||||
// Logical Operations
|
||||
def : Pat<(vnot_ppc v4i32:$vA), (VNOR $vA, $vA)>;
|
||||
|
||||
|
||||
@ -48,7 +48,9 @@ entry:
|
||||
%tmp = load <16 x i8>* %A
|
||||
%tmp2 = load <16 x i8>* %B
|
||||
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
|
||||
; CHECK: vmrglb
|
||||
; CHECK: lvx [[REG1:[0-9]+]]
|
||||
; CHECK: lvx [[REG2:[0-9]+]]
|
||||
; CHECK: vmrglb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
|
||||
store <16 x i8> %tmp3, <16 x i8>* %A
|
||||
ret void
|
||||
}
|
||||
@ -69,7 +71,9 @@ entry:
|
||||
%tmp = load <16 x i8>* %A
|
||||
%tmp2 = load <16 x i8>* %B
|
||||
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
|
||||
; CHECK: vmrghb
|
||||
; CHECK: lvx [[REG1:[0-9]+]]
|
||||
; CHECK: lvx [[REG2:[0-9]+]]
|
||||
; CHECK: vmrghb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
|
||||
store <16 x i8> %tmp3, <16 x i8>* %A
|
||||
ret void
|
||||
}
|
||||
@ -90,7 +94,9 @@ entry:
|
||||
%tmp = load <16 x i8>* %A
|
||||
%tmp2 = load <16 x i8>* %B
|
||||
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23>
|
||||
; CHECK: vmrglh
|
||||
; CHECK: lvx [[REG1:[0-9]+]]
|
||||
; CHECK: lvx [[REG2:[0-9]+]]
|
||||
; CHECK: vmrglh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
|
||||
store <16 x i8> %tmp3, <16 x i8>* %A
|
||||
ret void
|
||||
}
|
||||
@ -111,7 +117,9 @@ entry:
|
||||
%tmp = load <16 x i8>* %A
|
||||
%tmp2 = load <16 x i8>* %B
|
||||
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>
|
||||
; CHECK: vmrghh
|
||||
; CHECK: lvx [[REG1:[0-9]+]]
|
||||
; CHECK: lvx [[REG2:[0-9]+]]
|
||||
; CHECK: vmrghh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
|
||||
store <16 x i8> %tmp3, <16 x i8>* %A
|
||||
ret void
|
||||
}
|
||||
@ -132,7 +140,9 @@ entry:
|
||||
%tmp = load <16 x i8>* %A
|
||||
%tmp2 = load <16 x i8>* %B
|
||||
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23>
|
||||
; CHECK: vmrglw
|
||||
; CHECK: lvx [[REG1:[0-9]+]]
|
||||
; CHECK: lvx [[REG2:[0-9]+]]
|
||||
; CHECK: vmrglw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
|
||||
store <16 x i8> %tmp3, <16 x i8>* %A
|
||||
ret void
|
||||
}
|
||||
@ -153,7 +163,9 @@ entry:
|
||||
%tmp = load <16 x i8>* %A
|
||||
%tmp2 = load <16 x i8>* %B
|
||||
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
|
||||
; CHECK: vmrghw
|
||||
; CHECK: lvx [[REG1:[0-9]+]]
|
||||
; CHECK: lvx [[REG2:[0-9]+]]
|
||||
; CHECK: vmrghw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
|
||||
store <16 x i8> %tmp3, <16 x i8>* %A
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user