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Give Sparc instruction patterns direct types instead of register classes.
Also update the documentation since Sparc is the nicest backend, and used as an example in WritingAnLLVMBackend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177835 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
19209960b6
commit
15a3c18623
@ -760,7 +760,7 @@ target description file (``IntRegs``).
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def LDrr : F3_1 <3, 0b000000, (outs IntRegs:$dst), (ins MEMrr:$addr),
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"ld [$addr], $dst",
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[(set IntRegs:$dst, (load ADDRrr:$addr))]>;
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[(set i32:$dst, (load ADDRrr:$addr))]>;
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The fourth parameter is the input source, which uses the address operand
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``MEMrr`` that is defined earlier in ``SparcInstrInfo.td``:
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@ -788,7 +788,7 @@ class is defined:
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def LDri : F3_2 <3, 0b000000, (outs IntRegs:$dst), (ins MEMri:$addr),
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"ld [$addr], $dst",
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[(set IntRegs:$dst, (load ADDRri:$addr))]>;
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[(set i32:$dst, (load ADDRri:$addr))]>;
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Writing these definitions for so many similar instructions can involve a lot of
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cut and paste. In ``.td`` files, the ``multiclass`` directive enables the
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@ -803,11 +803,11 @@ pattern ``F3_12`` is defined to create 2 instruction classes each time
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def rr : F3_1 <2, Op3Val,
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(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
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!strconcat(OpcStr, " $b, $c, $dst"),
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[(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
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[(set i32:$dst, (OpNode i32:$b, i32:$c))]>;
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def ri : F3_2 <2, Op3Val,
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(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $b, $c, $dst"),
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[(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
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[(set i32:$dst, (OpNode i32:$b, simm13:$c))]>;
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}
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So when the ``defm`` directive is used for the ``XOR`` and ``ADD``
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@ -856,7 +856,7 @@ format instruction having three operands.
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def XNORrr : F3_1<2, 0b000111,
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(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
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"xnor $b, $c, $dst",
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[(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
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[(set i32:$dst, (not (xor i32:$b, i32:$c)))]>;
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The instruction templates in ``SparcInstrFormats.td`` show the base class for
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``F3_1`` is ``InstSP``.
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@ -1124,7 +1124,7 @@ a pattern with the store DAG operator.
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.. code-block:: llvm
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def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),
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"st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>;
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"st $src, [$addr]", [(store i32:$src, ADDRrr:$addr)]>;
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``ADDRrr`` is a memory mode that is also defined in ``SparcInstrInfo.td``:
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@ -1185,7 +1185,7 @@ instruction.
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SDValue CPTmp0;
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SDValue CPTmp1;
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// Pattern: (st:void IntRegs:i32:$src,
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// Pattern: (st:void i32:i32:$src,
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// ADDRrr:i32:$addr)<<P:Predicate_store>>
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// Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src)
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// Pattern complexity = 13 cost = 1 size = 0
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@ -182,11 +182,11 @@ multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
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def rr : F3_1<2, Op3Val,
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(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
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!strconcat(OpcStr, " $b, $c, $dst"),
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[(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
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[(set i32:$dst, (OpNode i32:$b, i32:$c))]>;
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def ri : F3_2<2, Op3Val,
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(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
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!strconcat(OpcStr, " $b, $c, $dst"),
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[(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
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[(set i32:$dst, (OpNode i32:$b, simm13:$c))]>;
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}
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/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
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@ -243,10 +243,10 @@ let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
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"!FpMOVD $src, $dst", []>;
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def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
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"!FpNEGD $src, $dst",
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[(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
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[(set f64:$dst, (fneg f64:$src))]>;
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def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
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"!FpABSD $src, $dst",
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[(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
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[(set f64:$dst, (fabs f64:$src))]>;
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}
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
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@ -257,19 +257,16 @@ let Uses = [ICC], usesCustomInserter = 1 in {
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def SELECT_CC_Int_ICC
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_ICC PSEUDO!",
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[(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F,
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imm:$Cond))]>;
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[(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
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def SELECT_CC_FP_ICC
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: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_FP_ICC PSEUDO!",
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[(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F,
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imm:$Cond))]>;
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[(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
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def SELECT_CC_DFP_ICC
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: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_DFP_ICC PSEUDO!",
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[(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F,
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imm:$Cond))]>;
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[(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
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}
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let usesCustomInserter = 1, Uses = [FCC] in {
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@ -277,19 +274,16 @@ let usesCustomInserter = 1, Uses = [FCC] in {
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def SELECT_CC_Int_FCC
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: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_FCC PSEUDO!",
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[(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F,
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imm:$Cond))]>;
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[(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
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def SELECT_CC_FP_FCC
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: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_FP_FCC PSEUDO!",
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[(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F,
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imm:$Cond))]>;
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[(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
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def SELECT_CC_DFP_FCC
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: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_DFP_FCC PSEUDO!",
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[(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F,
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imm:$Cond))]>;
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[(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
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}
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@ -309,111 +303,111 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
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def LDSBrr : F3_1<3, 0b001001,
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(outs IntRegs:$dst), (ins MEMrr:$addr),
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"ldsb [$addr], $dst",
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[(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>;
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[(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>;
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def LDSBri : F3_2<3, 0b001001,
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(outs IntRegs:$dst), (ins MEMri:$addr),
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"ldsb [$addr], $dst",
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[(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>;
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[(set i32:$dst, (sextloadi8 ADDRri:$addr))]>;
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def LDSHrr : F3_1<3, 0b001010,
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(outs IntRegs:$dst), (ins MEMrr:$addr),
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"ldsh [$addr], $dst",
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[(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>;
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[(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>;
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def LDSHri : F3_2<3, 0b001010,
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(outs IntRegs:$dst), (ins MEMri:$addr),
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"ldsh [$addr], $dst",
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[(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>;
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[(set i32:$dst, (sextloadi16 ADDRri:$addr))]>;
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def LDUBrr : F3_1<3, 0b000001,
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(outs IntRegs:$dst), (ins MEMrr:$addr),
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"ldub [$addr], $dst",
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[(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>;
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[(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>;
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def LDUBri : F3_2<3, 0b000001,
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(outs IntRegs:$dst), (ins MEMri:$addr),
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"ldub [$addr], $dst",
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[(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>;
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[(set i32:$dst, (zextloadi8 ADDRri:$addr))]>;
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def LDUHrr : F3_1<3, 0b000010,
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(outs IntRegs:$dst), (ins MEMrr:$addr),
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"lduh [$addr], $dst",
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[(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>;
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[(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>;
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def LDUHri : F3_2<3, 0b000010,
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(outs IntRegs:$dst), (ins MEMri:$addr),
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"lduh [$addr], $dst",
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[(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>;
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[(set i32:$dst, (zextloadi16 ADDRri:$addr))]>;
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def LDrr : F3_1<3, 0b000000,
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(outs IntRegs:$dst), (ins MEMrr:$addr),
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"ld [$addr], $dst",
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[(set IntRegs:$dst, (load ADDRrr:$addr))]>;
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[(set i32:$dst, (load ADDRrr:$addr))]>;
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def LDri : F3_2<3, 0b000000,
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(outs IntRegs:$dst), (ins MEMri:$addr),
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"ld [$addr], $dst",
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[(set IntRegs:$dst, (load ADDRri:$addr))]>;
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[(set i32:$dst, (load ADDRri:$addr))]>;
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// Section B.2 - Load Floating-point Instructions, p. 92
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def LDFrr : F3_1<3, 0b100000,
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(outs FPRegs:$dst), (ins MEMrr:$addr),
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"ld [$addr], $dst",
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[(set FPRegs:$dst, (load ADDRrr:$addr))]>;
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[(set f32:$dst, (load ADDRrr:$addr))]>;
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def LDFri : F3_2<3, 0b100000,
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(outs FPRegs:$dst), (ins MEMri:$addr),
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"ld [$addr], $dst",
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[(set FPRegs:$dst, (load ADDRri:$addr))]>;
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[(set f32:$dst, (load ADDRri:$addr))]>;
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def LDDFrr : F3_1<3, 0b100011,
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(outs DFPRegs:$dst), (ins MEMrr:$addr),
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"ldd [$addr], $dst",
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[(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
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[(set f64:$dst, (load ADDRrr:$addr))]>;
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def LDDFri : F3_2<3, 0b100011,
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(outs DFPRegs:$dst), (ins MEMri:$addr),
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"ldd [$addr], $dst",
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[(set DFPRegs:$dst, (load ADDRri:$addr))]>;
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[(set f64:$dst, (load ADDRri:$addr))]>;
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// Section B.4 - Store Integer Instructions, p. 95
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def STBrr : F3_1<3, 0b000101,
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(outs), (ins MEMrr:$addr, IntRegs:$src),
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"stb $src, [$addr]",
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[(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>;
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[(truncstorei8 i32:$src, ADDRrr:$addr)]>;
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def STBri : F3_2<3, 0b000101,
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(outs), (ins MEMri:$addr, IntRegs:$src),
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"stb $src, [$addr]",
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[(truncstorei8 IntRegs:$src, ADDRri:$addr)]>;
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[(truncstorei8 i32:$src, ADDRri:$addr)]>;
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def STHrr : F3_1<3, 0b000110,
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(outs), (ins MEMrr:$addr, IntRegs:$src),
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"sth $src, [$addr]",
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[(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>;
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[(truncstorei16 i32:$src, ADDRrr:$addr)]>;
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def STHri : F3_2<3, 0b000110,
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(outs), (ins MEMri:$addr, IntRegs:$src),
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"sth $src, [$addr]",
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[(truncstorei16 IntRegs:$src, ADDRri:$addr)]>;
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[(truncstorei16 i32:$src, ADDRri:$addr)]>;
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def STrr : F3_1<3, 0b000100,
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(outs), (ins MEMrr:$addr, IntRegs:$src),
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"st $src, [$addr]",
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[(store IntRegs:$src, ADDRrr:$addr)]>;
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[(store i32:$src, ADDRrr:$addr)]>;
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def STri : F3_2<3, 0b000100,
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(outs), (ins MEMri:$addr, IntRegs:$src),
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"st $src, [$addr]",
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[(store IntRegs:$src, ADDRri:$addr)]>;
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[(store i32:$src, ADDRri:$addr)]>;
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// Section B.5 - Store Floating-point Instructions, p. 97
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def STFrr : F3_1<3, 0b100100,
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(outs), (ins MEMrr:$addr, FPRegs:$src),
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"st $src, [$addr]",
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[(store FPRegs:$src, ADDRrr:$addr)]>;
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[(store f32:$src, ADDRrr:$addr)]>;
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def STFri : F3_2<3, 0b100100,
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(outs), (ins MEMri:$addr, FPRegs:$src),
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"st $src, [$addr]",
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[(store FPRegs:$src, ADDRri:$addr)]>;
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[(store f32:$src, ADDRri:$addr)]>;
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def STDFrr : F3_1<3, 0b100111,
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(outs), (ins MEMrr:$addr, DFPRegs:$src),
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"std $src, [$addr]",
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[(store DFPRegs:$src, ADDRrr:$addr)]>;
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[(store f64:$src, ADDRrr:$addr)]>;
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def STDFri : F3_2<3, 0b100111,
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(outs), (ins MEMri:$addr, DFPRegs:$src),
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"std $src, [$addr]",
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[(store DFPRegs:$src, ADDRri:$addr)]>;
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[(store f64:$src, ADDRri:$addr)]>;
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// Section B.9 - SETHI Instruction, p. 104
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def SETHIi: F2_1<0b100,
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(outs IntRegs:$dst), (ins i32imm:$src),
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"sethi $src, $dst",
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[(set IntRegs:$dst, SETHIimm:$src)]>;
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[(set i32:$dst, SETHIimm:$src)]>;
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// Section B.10 - NOP Instruction, p. 105
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// (It's a special case of SETHI)
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@ -426,7 +420,7 @@ defm AND : F3_12<"and", 0b000001, and>;
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def ANDNrr : F3_1<2, 0b000101,
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(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
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"andn $b, $c, $dst",
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[(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
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[(set i32:$dst, (and i32:$b, (not i32:$c)))]>;
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def ANDNri : F3_2<2, 0b000101,
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(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
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"andn $b, $c, $dst", []>;
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@ -436,7 +430,7 @@ defm OR : F3_12<"or", 0b000010, or>;
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def ORNrr : F3_1<2, 0b000110,
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(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
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"orn $b, $c, $dst",
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[(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
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[(set i32:$dst, (or i32:$b, (not i32:$c)))]>;
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def ORNri : F3_2<2, 0b000110,
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(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
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"orn $b, $c, $dst", []>;
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@ -445,7 +439,7 @@ defm XOR : F3_12<"xor", 0b000011, xor>;
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def XNORrr : F3_1<2, 0b000111,
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(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
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"xnor $b, $c, $dst",
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[(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
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[(set i32:$dst, (not (xor i32:$b, i32:$c)))]>;
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def XNORri : F3_2<2, 0b000111,
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(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
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"xnor $b, $c, $dst", []>;
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@ -462,7 +456,7 @@ defm ADD : F3_12<"add", 0b000000, add>;
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def LEA_ADDri : F3_2<2, 0b000000,
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(outs IntRegs:$dst), (ins MEMri:$addr),
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"add ${addr:arith}, $dst",
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[(set IntRegs:$dst, ADDRri:$addr)]>;
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[(set i32:$dst, ADDRri:$addr)]>;
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let Defs = [ICC] in
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defm ADDCC : F3_12<"addcc", 0b010000, addc>;
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@ -603,11 +597,11 @@ def FDTOI : F3_3<2, 0b110100, 0b011010010,
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def FSTOD : F3_3<2, 0b110100, 0b011001001,
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(outs DFPRegs:$dst), (ins FPRegs:$src),
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"fstod $src, $dst",
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[(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
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[(set f64:$dst, (fextend f32:$src))]>;
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def FDTOS : F3_3<2, 0b110100, 0b011000110,
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(outs FPRegs:$dst), (ins DFPRegs:$src),
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"fdtos $src, $dst",
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[(set FPRegs:$dst, (fround DFPRegs:$src))]>;
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[(set f32:$dst, (fround f64:$src))]>;
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// Floating-point Move Instructions, p. 144
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def FMOVS : F3_3<2, 0b110100, 0b000000001,
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@ -616,22 +610,22 @@ def FMOVS : F3_3<2, 0b110100, 0b000000001,
|
||||
def FNEGS : F3_3<2, 0b110100, 0b000000101,
|
||||
(outs FPRegs:$dst), (ins FPRegs:$src),
|
||||
"fnegs $src, $dst",
|
||||
[(set FPRegs:$dst, (fneg FPRegs:$src))]>;
|
||||
[(set f32:$dst, (fneg f32:$src))]>;
|
||||
def FABSS : F3_3<2, 0b110100, 0b000001001,
|
||||
(outs FPRegs:$dst), (ins FPRegs:$src),
|
||||
"fabss $src, $dst",
|
||||
[(set FPRegs:$dst, (fabs FPRegs:$src))]>;
|
||||
[(set f32:$dst, (fabs f32:$src))]>;
|
||||
|
||||
|
||||
// Floating-point Square Root Instructions, p.145
|
||||
def FSQRTS : F3_3<2, 0b110100, 0b000101001,
|
||||
(outs FPRegs:$dst), (ins FPRegs:$src),
|
||||
"fsqrts $src, $dst",
|
||||
[(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
|
||||
[(set f32:$dst, (fsqrt f32:$src))]>;
|
||||
def FSQRTD : F3_3<2, 0b110100, 0b000101010,
|
||||
(outs DFPRegs:$dst), (ins DFPRegs:$src),
|
||||
"fsqrtd $src, $dst",
|
||||
[(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
|
||||
[(set f64:$dst, (fsqrt f64:$src))]>;
|
||||
|
||||
|
||||
|
||||
@ -639,42 +633,42 @@ def FSQRTD : F3_3<2, 0b110100, 0b000101010,
|
||||
def FADDS : F3_3<2, 0b110100, 0b001000001,
|
||||
(outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
|
||||
"fadds $src1, $src2, $dst",
|
||||
[(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
|
||||
[(set f32:$dst, (fadd f32:$src1, f32:$src2))]>;
|
||||
def FADDD : F3_3<2, 0b110100, 0b001000010,
|
||||
(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
|
||||
"faddd $src1, $src2, $dst",
|
||||
[(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
|
||||
[(set f64:$dst, (fadd f64:$src1, f64:$src2))]>;
|
||||
def FSUBS : F3_3<2, 0b110100, 0b001000101,
|
||||
(outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
|
||||
"fsubs $src1, $src2, $dst",
|
||||
[(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
|
||||
[(set f32:$dst, (fsub f32:$src1, f32:$src2))]>;
|
||||
def FSUBD : F3_3<2, 0b110100, 0b001000110,
|
||||
(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
|
||||
"fsubd $src1, $src2, $dst",
|
||||
[(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
|
||||
[(set f64:$dst, (fsub f64:$src1, f64:$src2))]>;
|
||||
|
||||
// Floating-point Multiply and Divide Instructions, p. 147
|
||||
def FMULS : F3_3<2, 0b110100, 0b001001001,
|
||||
(outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
|
||||
"fmuls $src1, $src2, $dst",
|
||||
[(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
|
||||
[(set f32:$dst, (fmul f32:$src1, f32:$src2))]>;
|
||||
def FMULD : F3_3<2, 0b110100, 0b001001010,
|
||||
(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
|
||||
"fmuld $src1, $src2, $dst",
|
||||
[(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
|
||||
[(set f64:$dst, (fmul f64:$src1, f64:$src2))]>;
|
||||
def FSMULD : F3_3<2, 0b110100, 0b001101001,
|
||||
(outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
|
||||
"fsmuld $src1, $src2, $dst",
|
||||
[(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
|
||||
(fextend FPRegs:$src2)))]>;
|
||||
[(set f64:$dst, (fmul (fextend f32:$src1),
|
||||
(fextend f32:$src2)))]>;
|
||||
def FDIVS : F3_3<2, 0b110100, 0b001001101,
|
||||
(outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
|
||||
"fdivs $src1, $src2, $dst",
|
||||
[(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
|
||||
[(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>;
|
||||
def FDIVD : F3_3<2, 0b110100, 0b001001110,
|
||||
(outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
|
||||
"fdivd $src1, $src2, $dst",
|
||||
[(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
|
||||
[(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>;
|
||||
|
||||
// Floating-point Compare Instructions, p. 148
|
||||
// Note: the 2nd template arg is different for these guys.
|
||||
@ -685,11 +679,11 @@ let Defs = [FCC] in {
|
||||
def FCMPS : F3_3<2, 0b110101, 0b001010001,
|
||||
(outs), (ins FPRegs:$src1, FPRegs:$src2),
|
||||
"fcmps $src1, $src2\n\tnop",
|
||||
[(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>;
|
||||
[(SPcmpfcc f32:$src1, f32:$src2)]>;
|
||||
def FCMPD : F3_3<2, 0b110101, 0b001010010,
|
||||
(outs), (ins DFPRegs:$src1, DFPRegs:$src2),
|
||||
"fcmpd $src1, $src2\n\tnop",
|
||||
[(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>;
|
||||
[(SPcmpfcc f64:$src1, f64:$src2)]>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -704,52 +698,45 @@ let Predicates = [HasV9], Constraints = "$T = $dst" in {
|
||||
def MOVICCrr
|
||||
: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
|
||||
"mov$cc %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
|
||||
[(set i32:$dst, (SPselecticc i32:$F, i32:$T, imm:$cc))]>;
|
||||
def MOVICCri
|
||||
: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
|
||||
"mov$cc %icc, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>;
|
||||
[(set i32:$dst, (SPselecticc simm11:$F, i32:$T, imm:$cc))]>;
|
||||
}
|
||||
|
||||
let Uses = [FCC] in {
|
||||
def MOVFCCrr
|
||||
: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
|
||||
"mov$cc %fcc0, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
|
||||
[(set i32:$dst, (SPselectfcc i32:$F, i32:$T, imm:$cc))]>;
|
||||
def MOVFCCri
|
||||
: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
|
||||
"mov$cc %fcc0, $F, $dst",
|
||||
[(set IntRegs:$dst,
|
||||
(SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>;
|
||||
[(set i32:$dst, (SPselectfcc simm11:$F, i32:$T, imm:$cc))]>;
|
||||
}
|
||||
|
||||
let Uses = [ICC] in {
|
||||
def FMOVS_ICC
|
||||
: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
|
||||
"fmovs$cc %icc, $F, $dst",
|
||||
[(set FPRegs:$dst,
|
||||
(SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
|
||||
[(set f32:$dst,
|
||||
(SPselecticc f32:$F, f32:$T, imm:$cc))]>;
|
||||
def FMOVD_ICC
|
||||
: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
|
||||
"fmovd$cc %icc, $F, $dst",
|
||||
[(set DFPRegs:$dst,
|
||||
(SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
|
||||
[(set f64:$dst, (SPselecticc f64:$F, f64:$T, imm:$cc))]>;
|
||||
}
|
||||
|
||||
let Uses = [FCC] in {
|
||||
def FMOVS_FCC
|
||||
: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
|
||||
"fmovs$cc %fcc0, $F, $dst",
|
||||
[(set FPRegs:$dst,
|
||||
(SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
|
||||
[(set f32:$dst, (SPselectfcc f32:$F, f32:$T, imm:$cc))]>;
|
||||
def FMOVD_FCC
|
||||
: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
|
||||
"fmovd$cc %fcc0, $F, $dst",
|
||||
[(set DFPRegs:$dst,
|
||||
(SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
|
||||
[(set f64:$dst, (SPselectfcc f64:$F, f64:$T, imm:$cc))]>;
|
||||
}
|
||||
|
||||
}
|
||||
@ -762,11 +749,11 @@ let Predicates = [HasV9] in {
|
||||
def FNEGD : F3_3<2, 0b110100, 0b000000110,
|
||||
(outs DFPRegs:$dst), (ins DFPRegs:$src),
|
||||
"fnegd $src, $dst",
|
||||
[(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
|
||||
[(set f64:$dst, (fneg f64:$src))]>;
|
||||
def FABSD : F3_3<2, 0b110100, 0b000001010,
|
||||
(outs DFPRegs:$dst), (ins DFPRegs:$src),
|
||||
"fabsd $src, $dst",
|
||||
[(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
|
||||
[(set f64:$dst, (fabs f64:$src))]>;
|
||||
}
|
||||
|
||||
// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user