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Fix X86's isTruncateFree to not claim that truncate to i1 is free. This fixes Bill's testcase that failed for r48491.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48542 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -2383,6 +2383,31 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
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DAG.getConstant(Sum, N1C->getValueType(0)));
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}
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}
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// fold sra (shl X, m), result_size - n
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// -> (sign_extend (trunc (shl X, result_size - n - m))) for
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// result_size - n != m. If truncate is free for the target sext(shl) is
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// likely to result in better code.
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if (N0.getOpcode() == ISD::SHL) {
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// Get the two constanst of the shifts, CN0 = m, CN = n.
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const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
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if (N01C && N1C) {
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// Determine if the truncate type's bitsize would correspond to
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// an integer type for this target.
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unsigned VTValSize = MVT::getSizeInBits(VT);
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MVT::ValueType TruncVT = MVT::getIntegerType(VTValSize - N1C->getValue());
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unsigned ShiftAmt = N1C->getValue() - N01C->getValue();
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// If the shift wouldn't be a noop, the truncated type is an actual type,
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// and the truncate is free, then proceed with the transform.
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if (ShiftAmt != 0 && TLI.isTruncateFree(VT, TruncVT)) {
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SDOperand Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy());
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SDOperand Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt);
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SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift);
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return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc);
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}
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}
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}
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// Simplify, based on bits shifted out of the LHS.
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if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
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