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add new --gen-instr-desc option

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7545 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2003-08-03 21:58:28 +00:00
parent 0969c5bdf2
commit 15de32d706
2 changed files with 12 additions and 2 deletions
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7
support/tools/TableGen/TableGen.cpp
View File

@ -22,7 +22,7 @@ enum ActionType {
PrintRecords,
GenEmitter,
GenRegisterEnums, GenRegister, GenRegisterHeader,
GenInstrEnums,
GenInstrEnums, GenInstrs,
PrintEnums,
Parse,
};
@ -42,6 +42,8 @@ namespace {
"Generate a register info description header"),
clEnumValN(GenInstrEnums, "gen-instr-enums",
"Generate enum values for instructions"),
clEnumValN(GenInstrs, "gen-instr-desc",
"Generate instruction descriptions"),
clEnumValN(PrintEnums, "print-enums",
"Print enum values for a class"),
clEnumValN(Parse, "parse",
@ -435,6 +437,9 @@ int main(int argc, char **argv) {
case GenInstrEnums:
InstrInfoEmitter(Records).runEnums(*Out);
break;
case GenInstrs:
InstrInfoEmitter(Records).run(*Out);
break;
case PrintEnums:
std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);

7
utils/TableGen/TableGen.cpp
View File

@ -22,7 +22,7 @@ enum ActionType {
PrintRecords,
GenEmitter,
GenRegisterEnums, GenRegister, GenRegisterHeader,
GenInstrEnums,
GenInstrEnums, GenInstrs,
PrintEnums,
Parse,
};
@ -42,6 +42,8 @@ namespace {
"Generate a register info description header"),
clEnumValN(GenInstrEnums, "gen-instr-enums",
"Generate enum values for instructions"),
clEnumValN(GenInstrs, "gen-instr-desc",
"Generate instruction descriptions"),
clEnumValN(PrintEnums, "print-enums",
"Print enum values for a class"),
clEnumValN(Parse, "parse",
@ -435,6 +437,9 @@ int main(int argc, char **argv) {
case GenInstrEnums:
InstrInfoEmitter(Records).runEnums(*Out);
break;
case GenInstrs:
InstrInfoEmitter(Records).run(*Out);
break;
case PrintEnums:
std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);