From 15f96db4d91eba096b7eaa36d8f891131412e064 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Sun, 15 Dec 2002 21:02:20 +0000
Subject: [PATCH] Add a big assert making sure 2 address instructions are
 formed right

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5057 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/RegAllocSimple.cpp | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 97b42b0307a..17b1044c5ce 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -379,6 +379,12 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
             if (TM.getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) {
               // must be same register number as the first operand
               // This maps a = b + c into b += c, and saves b into a's spot
+              assert(MI->getOperand(1).isRegister()  &&
+                     MI->getOperand(1).getAllocatedRegNum() &&
+                     MF->getRegClass(virtualReg) ==
+                       PhysRegClasses[MI->getOperand(1).getAllocatedRegNum()] &&
+                     "Two address instruction invalid!");
+
               physReg = MI->getOperand(1).getAllocatedRegNum();
             } else {
               physReg = getFreeReg(virtualReg);