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Change the interface to the type legalization method

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ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60348 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands
2008-12-01 11:39:25 +00:00
parent d54d86038d
commit 1607f05cb7
20 changed files with 377 additions and 378 deletions
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21
lib/Target/XCore/XCoreISelLowering.cpp
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@@ -161,7 +161,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) {
case ISD::VASTART: return LowerVASTART(Op, DAG);
// FIXME: Remove these when LegalizeDAGTypes lands.
case ISD::ADD:
case ISD::SUB: return SDValue(ExpandADDSUB(Op.getNode(), DAG),0);
case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
default:
assert(0 && "unimplemented operand");
@@ -169,16 +169,19 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) {
}
}
/// ReplaceNodeResults - Provide custom lowering hooks for nodes with illegal
/// result types.
SDNode *XCoreTargetLowering::
ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
/// ReplaceNodeResults - Replace the results of node with an illegal result
/// type with new values built out of custom code.
void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) {
switch (N->getOpcode()) {
default:
assert(0 && "Don't know how to custom expand this!");
return NULL;
return;
case ISD::ADD:
case ISD::SUB: return ExpandADDSUB(N, DAG);
case ISD::SUB:
Results.push_back(ExpandADDSUB(N, DAG));
return;
}
}
@@ -296,7 +299,7 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG)
return DAG.getNode(XCoreISD::DPRelativeWrapper, MVT::i32, JTI);
}
SDNode *XCoreTargetLowering::
SDValue XCoreTargetLowering::
ExpandADDSUB(SDNode *N, SelectionDAG &DAG)
{
assert(N->getValueType(0) == MVT::i64 &&
@@ -326,7 +329,7 @@ ExpandADDSUB(SDNode *N, SelectionDAG &DAG)
LHSH, RHSH, Carry);
SDValue Hi(Ignored.getNode(), 1);
// Merge the pieces
return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).getNode();
return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
}
SDValue XCoreTargetLowering::