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Refactor a few ARM load instructions to better parameterize things and re-use

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119598 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-11-18 00:46:58 +00:00
parent 424216453f
commit 160f8f0e67
2 changed files with 51 additions and 115 deletions
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140
lib/Target/ARM/ARMInstrFormats.td
View File

@ -500,109 +500,45 @@ class AXI3<dag oops, dag iops, Format f, InstrItinClass itin,
: XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
asm, "", pattern>;
class AI3ld<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
opc, asm, "", pattern> {
bits<14> addr;
bits<4> Rt;
let Inst{27-25} = 0b000;
let Inst{24} = 1; // P bit
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{21} = 0; // W bit
let Inst{20} = 1; // L bit
let Inst{19-16} = addr{12-9}; // Rn
let Inst{15-12} = Rt; // Rt
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{7-4} = op;
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
}
class AXI3ld<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
string asm, list<dag> pattern>
: XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
asm, "", pattern> {
bits<14> addr;
bits<4> Rt;
let Inst{27-25} = 0b000;
let Inst{24} = 1; // P bit
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{21} = 0; // W bit
let Inst{20} = 1; // L bit
let Inst{19-16} = addr{12-9}; // Rn
let Inst{15-12} = Rt; // Rt
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{7-4} = op;
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
}
// loads
class AI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
opc, asm, "", pattern> {
bits<14> addr;
bits<4> Rt;
let Inst{27-25} = 0b000;
let Inst{24} = 1; // P bit
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{21} = 0; // W bit
let Inst{20} = 1; // L bit
let Inst{19-16} = addr{12-9}; // Rn
let Inst{15-12} = Rt; // Rt
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{7-4} = 0b1011;
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
}
class AXI3ldh<dag oops, dag iops, Format f, InstrItinClass itin,
string asm, list<dag> pattern>
: XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
asm, "", pattern> {
bits<14> addr;
bits<4> Rt;
let Inst{27-25} = 0b000;
let Inst{24} = 1; // P bit
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{21} = 0; // W bit
let Inst{20} = 1; // L bit
let Inst{19-16} = addr{12-9}; // Rn
let Inst{15-12} = Rt; // Rt
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{7-4} = 0b1011;
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
}
class AI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
opc, asm, "", pattern> {
bits<14> addr;
bits<4> Rt;
let Inst{27-25} = 0b000;
let Inst{24} = 1; // P bit
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{21} = 0; // W bit
let Inst{20} = 1; // L bit
let Inst{19-16} = addr{12-9}; // Rn
let Inst{15-12} = Rt; // Rt
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{7-4} = 0b1111;
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
}
class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
string asm, list<dag> pattern>
: XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
asm, "", pattern> {
bits<14> addr;
bits<4> Rt;
let Inst{27-25} = 0b000;
let Inst{24} = 1; // P bit
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{21} = 0; // W bit
let Inst{20} = 1; // L bit
let Inst{19-16} = addr{12-9}; // Rn
let Inst{15-12} = Rt; // Rt
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{7-4} = 0b1111;
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
}
class AI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
opc, asm, "", pattern> {
bits<14> addr;
bits<4> Rt;
let Inst{27-25} = 0b000;
let Inst{24} = 1; // P bit
let Inst{23} = addr{8}; // U bit
let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
let Inst{21} = 0; // W bit
let Inst{20} = 1; // L bit
let Inst{19-16} = addr{12-9}; // Rn
let Inst{15-12} = Rt; // Rt
let Inst{11-8} = addr{7-4}; // imm7_4/zero
let Inst{7-4} = 0b1101;
let Inst{3-0} = addr{3-0}; // imm3_0/Rm
}
class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
string asm, list<dag> pattern>
: XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
asm, "", pattern> {
let Inst{4} = 1;
let Inst{5} = 0; // H bit
let Inst{6} = 1; // S bit
let Inst{7} = 1;
let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit
}
class AI3ldd<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,

26
lib/Target/ARM/ARMInstrInfo.td
View File

@ -1134,21 +1134,21 @@ def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_r, "",
[(set GPR:$dst, (load addrmodepc:$addr))]>;
def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
def PICLDRH : AXI3ld<0b1011, (outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_bh_r, "",
[(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
def PICLDRB : AXI2ldb<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_bh_r, "",
[(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
[(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_bh_r, "",
[(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
def PICLDRSH : AXI3ld<0b1111, (outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_bh_r, "",
[(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
[(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
def PICLDRSB : AXI3ld<0b1101, (outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
Pseudo, IIC_iLoad_bh_r, "",
[(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
[(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
}
let AddedComplexity = 10 in {
def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
@ -1549,16 +1549,16 @@ def LDRcp : AIldst1<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
}
// Loads with zero extension
def LDRH : AI3ldh<(outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
def LDRH : AI3ld<0b1011, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
[(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
// Loads with sign extension
def LDRSH : AI3ldsh<(outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
def LDRSH : AI3ld<0b1111, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
[(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
def LDRSB : AI3ldsb<(outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
def LDRSB : AI3ld<0b1101, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
[(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;