From 161e897b0fb35d156b2fe720fadabd975b0d6723 Mon Sep 17 00:00:00 2001 From: Dale Johannesen Date: Fri, 5 Oct 2007 20:04:43 +0000 Subject: [PATCH] First round of ppc long double. call/return and basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42644 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/RuntimeLibcalls.h | 27 ++++-- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 87 +++++++++++++------ lib/CodeGen/SelectionDAG/TargetLowering.cpp | 30 +++++-- lib/Target/PowerPC/PPCCallingConv.td | 3 +- lib/Target/PowerPC/PPCISelLowering.cpp | 14 +++- test/CodeGen/PowerPC/ppcf128-1-opt.ll | 29 +++++++ test/CodeGen/PowerPC/ppcf128-1.ll | 92 +++++++++++++++++++++ 7 files changed, 240 insertions(+), 42 deletions(-) create mode 100644 test/CodeGen/PowerPC/ppcf128-1-opt.ll create mode 100644 test/CodeGen/PowerPC/ppcf128-1.ll diff --git a/include/llvm/CodeGen/RuntimeLibcalls.h b/include/llvm/CodeGen/RuntimeLibcalls.h index 80cc33a0bc7..5327d68106a 100644 --- a/include/llvm/CodeGen/RuntimeLibcalls.h +++ b/include/llvm/CodeGen/RuntimeLibcalls.h @@ -18,9 +18,8 @@ namespace llvm { namespace RTLIB { /// RTLIB::Libcall enum - This enum defines all of the runtime library calls - /// the backend can emit. "LD" is used for all long double types, since - /// these functions will have the same interface on different targets even - /// though the data is not in the same format. + /// the backend can emit. The various long double types cannot be merged, + /// because 80-bit library functions use "xf" and 128-bit use "tf". /// enum Libcall { // Integer @@ -46,22 +45,29 @@ namespace RTLIB { // FLOATING POINT ADD_F32, ADD_F64, + ADD_PPCF128, SUB_F32, SUB_F64, + SUB_PPCF128, MUL_F32, MUL_F64, + MUL_PPCF128, DIV_F32, DIV_F64, + DIV_PPCF128, REM_F32, REM_F64, + REM_PPCF128, NEG_F32, NEG_F64, POWI_F32, POWI_F64, - POWI_LD, + POWI_F80, + POWI_PPCF128, SQRT_F32, SQRT_F64, - SQRT_LD, + SQRT_F80, + SQRT_PPCF128, SIN_F32, SIN_F64, COS_F32, @@ -74,18 +80,21 @@ namespace RTLIB { FPTOSINT_F32_I64, FPTOSINT_F64_I32, FPTOSINT_F64_I64, - FPTOSINT_LD_I64, + FPTOSINT_F80_I64, + FPTOSINT_PPCF128_I64, FPTOUINT_F32_I32, FPTOUINT_F32_I64, FPTOUINT_F64_I32, FPTOUINT_F64_I64, - FPTOUINT_LD_I32, - FPTOUINT_LD_I64, + FPTOUINT_F80_I32, + FPTOUINT_F80_I64, + FPTOUINT_PPCF128_I64, SINTTOFP_I32_F32, SINTTOFP_I32_F64, SINTTOFP_I64_F32, SINTTOFP_I64_F64, - SINTTOFP_I64_LD, + SINTTOFP_I64_F80, + SINTTOFP_I64_PPCF128, UINTTOFP_I32_F32, UINTTOFP_I32_F64, UINTTOFP_I64_F32, diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index e0f2f7a9456..d55a4da28e4 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -3055,7 +3055,10 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { switch(Node->getOpcode()) { case ISD::FSQRT: LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : - VT == MVT::f64 ? RTLIB::SQRT_F64 : RTLIB::SQRT_LD; + VT == MVT::f64 ? RTLIB::SQRT_F64 : + VT == MVT::f80 ? RTLIB::SQRT_F80 : + VT == MVT::ppcf128 ? RTLIB::SQRT_PPCF128 : + RTLIB::UNKNOWN_LIBCALL; break; case ISD::FSIN: LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64; @@ -3079,7 +3082,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32 ? RTLIB::POWI_F32 : Node->getValueType(0) == MVT::f64 ? RTLIB::POWI_F64 : - RTLIB::POWI_LD; + Node->getValueType(0) == MVT::f80 ? RTLIB::POWI_F80 : + Node->getValueType(0) == MVT::ppcf128 ? RTLIB::POWI_PPCF128 : + RTLIB::UNKNOWN_LIBCALL; SDOperand Dummy; Result = ExpandLibCall(TLI.getLibcallName(LC), Node, false/*sign irrelevant*/, Dummy); @@ -3261,9 +3266,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { else if (OVT == MVT::f64) LC = (VT == MVT::i32) ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; - else if (OVT == MVT::f80 || OVT == MVT::f128 || OVT == MVT::ppcf128) { + else if (OVT == MVT::f80) { assert(VT == MVT::i64); - LC = RTLIB::FPTOSINT_LD_I64; + LC = RTLIB::FPTOSINT_F80_I64; + } + else if (OVT == MVT::ppcf128) { + assert(VT == MVT::i64); + LC = RTLIB::FPTOSINT_PPCF128_I64; } break; } @@ -3275,9 +3284,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { else if (OVT == MVT::f64) LC = (VT == MVT::i32) ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; - else if (OVT == MVT::f80 || OVT == MVT::f128 || OVT == MVT::ppcf128) { + else if (OVT == MVT::f80) { LC = (VT == MVT::i32) - ? RTLIB::FPTOUINT_LD_I32 : RTLIB::FPTOUINT_LD_I64; + ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64; + } + else if (OVT == MVT::ppcf128) { + assert(VT == MVT::i64); + LC = RTLIB::FPTOUINT_PPCF128_I64; } break; } @@ -5375,13 +5388,15 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ } } - RTLIB::Libcall LC; + RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; if (Node->getOperand(0).getValueType() == MVT::f32) LC = RTLIB::FPTOSINT_F32_I64; else if (Node->getOperand(0).getValueType() == MVT::f64) LC = RTLIB::FPTOSINT_F64_I64; - else - LC = RTLIB::FPTOSINT_LD_I64; + else if (Node->getOperand(0).getValueType() == MVT::f80) + LC = RTLIB::FPTOSINT_F80_I64; + else if (Node->getOperand(0).getValueType() == MVT::ppcf128) + LC = RTLIB::FPTOSINT_PPCF128_I64; Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false/*sign irrelevant*/, Hi); break; @@ -5410,10 +5425,10 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ LC = RTLIB::FPTOUINT_F32_I64; else if (Node->getOperand(0).getValueType() == MVT::f64) LC = RTLIB::FPTOUINT_F64_I64; - else if (Node->getOperand(0).getValueType() == MVT::f80 || - Node->getOperand(0).getValueType() == MVT::f128 || - Node->getOperand(0).getValueType() == MVT::ppcf128) - LC = RTLIB::FPTOUINT_LD_I64; + else if (Node->getOperand(0).getValueType() == MVT::f80) + LC = RTLIB::FPTOUINT_F80_I64; + else if (Node->getOperand(0).getValueType() == MVT::ppcf128) + LC = RTLIB::FPTOUINT_PPCF128_I64; Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false/*sign irrelevant*/, Hi); break; @@ -5679,23 +5694,35 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ break; case ISD::FADD: - Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) - ? RTLIB::ADD_F32 : RTLIB::ADD_F64), + Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::ADD_F32 : + VT == MVT::f64 ? RTLIB::ADD_F64 : + VT == MVT::ppcf128 ? + RTLIB::ADD_PPCF128 : + RTLIB::UNKNOWN_LIBCALL), Node, false, Hi); break; case ISD::FSUB: - Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) - ? RTLIB::SUB_F32 : RTLIB::SUB_F64), + Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::SUB_F32 : + VT == MVT::f64 ? RTLIB::SUB_F64 : + VT == MVT::ppcf128 ? + RTLIB::SUB_PPCF128 : + RTLIB::UNKNOWN_LIBCALL), Node, false, Hi); break; case ISD::FMUL: - Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) - ? RTLIB::MUL_F32 : RTLIB::MUL_F64), + Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::MUL_F32 : + VT == MVT::f64 ? RTLIB::MUL_F64 : + VT == MVT::ppcf128 ? + RTLIB::MUL_PPCF128 : + RTLIB::UNKNOWN_LIBCALL), Node, false, Hi); break; case ISD::FDIV: - Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) - ? RTLIB::DIV_F32 : RTLIB::DIV_F64), + Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::DIV_F32 : + VT == MVT::f64 ? RTLIB::DIV_F64 : + VT == MVT::ppcf128 ? + RTLIB::DIV_PPCF128 : + RTLIB::UNKNOWN_LIBCALL), Node, false, Hi); break; case ISD::FP_EXTEND: @@ -5707,7 +5734,10 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ case ISD::FPOWI: Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) ? RTLIB::POWI_F32 : (VT == MVT::f64) ? RTLIB::POWI_F64 : - RTLIB::POWI_LD), + (VT == MVT::f80) ? RTLIB::POWI_F80 : + (VT == MVT::ppcf128) ? + RTLIB::POWI_PPCF128 : + RTLIB::UNKNOWN_LIBCALL), Node, false, Hi); break; case ISD::FSQRT: @@ -5717,7 +5747,10 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ switch(Node->getOpcode()) { case ISD::FSQRT: LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : - (VT == MVT::f64) ? RTLIB::SQRT_F64 : RTLIB::SQRT_LD; + (VT == MVT::f64) ? RTLIB::SQRT_F64 : + (VT == MVT::f80) ? RTLIB::SQRT_F80 : + (VT == MVT::ppcf128) ? RTLIB::SQRT_PPCF128 : + RTLIB::UNKNOWN_LIBCALL; break; case ISD::FSIN: LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64; @@ -5768,9 +5801,13 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; else if (VT == MVT::f64) LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; - else if (VT == MVT::f80 || VT == MVT::f128 || VT == MVT::ppcf128) { + else if (VT == MVT::f80) { assert(isSigned); - LC = RTLIB::SINTTOFP_I64_LD; + LC = RTLIB::SINTTOFP_I64_F80; + } + else if (VT == MVT::ppcf128) { + assert(isSigned); + LC = RTLIB::SINTTOFP_I64_PPCF128; } } else { if (VT == MVT::f32) diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index f87ebe40a12..e00f2f08e4b 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -46,22 +46,29 @@ static void InitLibcallNames(const char **Names) { Names[RTLIB::NEG_I64] = "__negdi2"; Names[RTLIB::ADD_F32] = "__addsf3"; Names[RTLIB::ADD_F64] = "__adddf3"; + Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; Names[RTLIB::SUB_F32] = "__subsf3"; Names[RTLIB::SUB_F64] = "__subdf3"; + Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; Names[RTLIB::MUL_F32] = "__mulsf3"; Names[RTLIB::MUL_F64] = "__muldf3"; + Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; Names[RTLIB::DIV_F32] = "__divsf3"; Names[RTLIB::DIV_F64] = "__divdf3"; + Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; Names[RTLIB::REM_F32] = "fmodf"; Names[RTLIB::REM_F64] = "fmod"; + Names[RTLIB::REM_PPCF128] = "fmodl"; Names[RTLIB::NEG_F32] = "__negsf2"; Names[RTLIB::NEG_F64] = "__negdf2"; Names[RTLIB::POWI_F32] = "__powisf2"; Names[RTLIB::POWI_F64] = "__powidf2"; - Names[RTLIB::POWI_LD] = "__powixf2"; + Names[RTLIB::POWI_F80] = "__powixf2"; + Names[RTLIB::POWI_PPCF128] = "__powitf2"; Names[RTLIB::SQRT_F32] = "sqrtf"; Names[RTLIB::SQRT_F64] = "sqrt"; - Names[RTLIB::SQRT_LD] = "sqrtl"; + Names[RTLIB::SQRT_F80] = "sqrtl"; + Names[RTLIB::SQRT_PPCF128] = "sqrtl"; Names[RTLIB::SIN_F32] = "sinf"; Names[RTLIB::SIN_F64] = "sin"; Names[RTLIB::COS_F32] = "cosf"; @@ -72,18 +79,21 @@ static void InitLibcallNames(const char **Names) { Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; - Names[RTLIB::FPTOSINT_LD_I64] = "__fixxfdi"; + Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; + Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; - Names[RTLIB::FPTOUINT_LD_I32] = "__fixunsxfsi"; - Names[RTLIB::FPTOUINT_LD_I64] = "__fixunsxfdi"; + Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; + Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; + Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; - Names[RTLIB::SINTTOFP_I64_LD] = "__floatdixf"; + Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; + Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; @@ -222,6 +232,14 @@ void TargetLowering::computeRegisterProperties() { } } + // ppcf128 type is really two f64's. + if (!isTypeLegal(MVT::ppcf128)) { + NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; + RegisterTypeForVT[MVT::ppcf128] = MVT::f64; + TransformToType[MVT::ppcf128] = MVT::f64; + ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); + } + // Decide how to handle f64. If the target does not have native f64 support, // expand it to i64 and we will be generating soft float library calls. if (!isTypeLegal(MVT::f64)) { diff --git a/lib/Target/PowerPC/PPCCallingConv.td b/lib/Target/PowerPC/PPCCallingConv.td index 9e31b5a6690..0991d8397c7 100644 --- a/lib/Target/PowerPC/PPCCallingConv.td +++ b/lib/Target/PowerPC/PPCCallingConv.td @@ -25,7 +25,8 @@ def RetCC_PPC : CallingConv<[ CCIfType<[i32], CCAssignToReg<[R3, R4]>>, CCIfType<[i64], CCAssignToReg<[X3, X4]>>, - CCIfType<[f32, f64], CCAssignToReg<[F1]>>, + CCIfType<[f32], CCAssignToReg<[F1]>>, + CCIfType<[f64], CCAssignToReg<[F1, F2]>>, // Vector types are always returned in V2. CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>> diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index cfebef1edd6..ec1046fcb14 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1812,8 +1812,20 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, NumResults = 1; NodeTys.push_back(MVT::i64); break; - case MVT::f32: case MVT::f64: + if (Op.Val->getValueType(1) == MVT::f64) { + Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1); + ResultVals[0] = Chain.getValue(0); + Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64, + Chain.getValue(2)).getValue(1); + ResultVals[1] = Chain.getValue(0); + NumResults = 2; + NodeTys.push_back(MVT::f64); + NodeTys.push_back(MVT::f64); + break; + } + // else fall through + case MVT::f32: Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0), InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); diff --git a/test/CodeGen/PowerPC/ppcf128-1-opt.ll b/test/CodeGen/PowerPC/ppcf128-1-opt.ll new file mode 100644 index 00000000000..5c059b4ea29 --- /dev/null +++ b/test/CodeGen/PowerPC/ppcf128-1-opt.ll @@ -0,0 +1,29 @@ +; RUN: llvm-as < %s | llc > %t +; ModuleID = '' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin8" + +define ppc_fp128 @plus(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %tmp3 = add ppc_fp128 %x, %y ; [#uses=1] + ret ppc_fp128 %tmp3 +} + +define ppc_fp128 @minus(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %tmp3 = sub ppc_fp128 %x, %y ; [#uses=1] + ret ppc_fp128 %tmp3 +} + +define ppc_fp128 @times(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %tmp3 = mul ppc_fp128 %x, %y ; [#uses=1] + ret ppc_fp128 %tmp3 +} + +define ppc_fp128 @divide(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %tmp3 = fdiv ppc_fp128 %x, %y ; [#uses=1] + ret ppc_fp128 %tmp3 +} + diff --git a/test/CodeGen/PowerPC/ppcf128-1.ll b/test/CodeGen/PowerPC/ppcf128-1.ll new file mode 100644 index 00000000000..ea8dd37c97d --- /dev/null +++ b/test/CodeGen/PowerPC/ppcf128-1.ll @@ -0,0 +1,92 @@ +; RUN: llvm-as < %s | opt -std-compile-opts | llc > %t +; ModuleID = 'ld3.c' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin8" + +define ppc_fp128 @plus(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %x_addr = alloca ppc_fp128 ; [#uses=2] + %y_addr = alloca ppc_fp128 ; [#uses=2] + %retval = alloca ppc_fp128, align 16 ; [#uses=2] + %tmp = alloca ppc_fp128, align 16 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store ppc_fp128 %x, ppc_fp128* %x_addr + store ppc_fp128 %y, ppc_fp128* %y_addr + %tmp1 = load ppc_fp128* %x_addr, align 16 ; [#uses=1] + %tmp2 = load ppc_fp128* %y_addr, align 16 ; [#uses=1] + %tmp3 = add ppc_fp128 %tmp1, %tmp2 ; [#uses=1] + store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16 + %tmp4 = load ppc_fp128* %tmp, align 16 ; [#uses=1] + store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16 + br label %return + +return: ; preds = %entry + %retval5 = load ppc_fp128* %retval ; [#uses=1] + ret ppc_fp128 %retval5 +} + +define ppc_fp128 @minus(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %x_addr = alloca ppc_fp128 ; [#uses=2] + %y_addr = alloca ppc_fp128 ; [#uses=2] + %retval = alloca ppc_fp128, align 16 ; [#uses=2] + %tmp = alloca ppc_fp128, align 16 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store ppc_fp128 %x, ppc_fp128* %x_addr + store ppc_fp128 %y, ppc_fp128* %y_addr + %tmp1 = load ppc_fp128* %x_addr, align 16 ; [#uses=1] + %tmp2 = load ppc_fp128* %y_addr, align 16 ; [#uses=1] + %tmp3 = sub ppc_fp128 %tmp1, %tmp2 ; [#uses=1] + store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16 + %tmp4 = load ppc_fp128* %tmp, align 16 ; [#uses=1] + store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16 + br label %return + +return: ; preds = %entry + %retval5 = load ppc_fp128* %retval ; [#uses=1] + ret ppc_fp128 %retval5 +} + +define ppc_fp128 @times(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %x_addr = alloca ppc_fp128 ; [#uses=2] + %y_addr = alloca ppc_fp128 ; [#uses=2] + %retval = alloca ppc_fp128, align 16 ; [#uses=2] + %tmp = alloca ppc_fp128, align 16 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store ppc_fp128 %x, ppc_fp128* %x_addr + store ppc_fp128 %y, ppc_fp128* %y_addr + %tmp1 = load ppc_fp128* %x_addr, align 16 ; [#uses=1] + %tmp2 = load ppc_fp128* %y_addr, align 16 ; [#uses=1] + %tmp3 = mul ppc_fp128 %tmp1, %tmp2 ; [#uses=1] + store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16 + %tmp4 = load ppc_fp128* %tmp, align 16 ; [#uses=1] + store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16 + br label %return + +return: ; preds = %entry + %retval5 = load ppc_fp128* %retval ; [#uses=1] + ret ppc_fp128 %retval5 +} + +define ppc_fp128 @divide(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %x_addr = alloca ppc_fp128 ; [#uses=2] + %y_addr = alloca ppc_fp128 ; [#uses=2] + %retval = alloca ppc_fp128, align 16 ; [#uses=2] + %tmp = alloca ppc_fp128, align 16 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store ppc_fp128 %x, ppc_fp128* %x_addr + store ppc_fp128 %y, ppc_fp128* %y_addr + %tmp1 = load ppc_fp128* %x_addr, align 16 ; [#uses=1] + %tmp2 = load ppc_fp128* %y_addr, align 16 ; [#uses=1] + %tmp3 = fdiv ppc_fp128 %tmp1, %tmp2 ; [#uses=1] + store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16 + %tmp4 = load ppc_fp128* %tmp, align 16 ; [#uses=1] + store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16 + br label %return + +return: ; preds = %entry + %retval5 = load ppc_fp128* %retval ; [#uses=1] + ret ppc_fp128 %retval5 +}