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R600/SI: Minor cleanup of function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219616 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1211,26 +1211,28 @@ bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
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void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
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MachineBasicBlock::iterator I = MI;
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MachineBasicBlock *MBB = MI->getParent();
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MachineOperand &MO = MI->getOperand(OpIdx);
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MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
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const TargetRegisterClass *RC = RI.getRegClass(RCID);
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unsigned Opcode = AMDGPU::V_MOV_B32_e32;
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if (MO.isReg()) {
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if (MO.isReg())
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Opcode = AMDGPU::COPY;
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} else if (RI.isSGPRClass(RC)) {
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else if (RI.isSGPRClass(RC))
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Opcode = AMDGPU::S_MOV_B32;
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}
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const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
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if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) {
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if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
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VRC = &AMDGPU::VReg_64RegClass;
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} else {
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else
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VRC = &AMDGPU::VReg_32RegClass;
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}
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unsigned Reg = MRI.createVirtualRegister(VRC);
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BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
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Reg).addOperand(MO);
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DebugLoc DL = MBB->findDebugLoc(I);
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BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg)
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.addOperand(MO);
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MO.ChangeToRegister(Reg, false);
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}
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