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[SystemZ] Add NC, OC and XC
For now these are just used to handle scalar ANDs, ORs and XORs in which all operands are memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190041 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -290,8 +290,15 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
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SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0,
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uint64_t UpperVal, uint64_t LowerVal);
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// N is a (store (load Y), X) pattern. Return true if it can use an MVC
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// from Y to X.
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bool storeLoadCanUseMVC(SDNode *N) const;
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// N is a (store (op (load A[0]), (load A[1])), X) pattern. Return true
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// if A[1 - I] == X and if N can use a block operation like NC from A[I]
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// to X.
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bool storeLoadCanUseBlockBinary(SDNode *N, unsigned I) const;
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public:
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SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(TM, OptLevel),
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@ -925,34 +932,27 @@ SDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node,
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return Or.getNode();
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}
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// N is a (store (load ...), ...) pattern. Return true if it can use MVC.
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bool SystemZDAGToDAGISel::storeLoadCanUseMVC(SDNode *N) const {
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StoreSDNode *Store = cast<StoreSDNode>(N);
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LoadSDNode *Load = cast<LoadSDNode>(Store->getValue().getNode());
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// MVC is logically a bytewise copy, so can't be used for volatile accesses.
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if (Load->isVolatile() || Store->isVolatile())
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// Return true if Load and Store:
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// - are loads and stores of the same size;
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// - do not partially overlap; and
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// - can be decomposed into what are logically individual character accesses
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// without changing the semantics.
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static bool canUseBlockOperation(StoreSDNode *Store, LoadSDNode *Load,
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AliasAnalysis *AA) {
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// Check that the two memory operands have the same size.
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if (Load->getMemoryVT() != Store->getMemoryVT())
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return false;
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// Prefer not to use MVC if either address can use ... RELATIVE LONG
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// instructions.
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assert(Load->getMemoryVT() == Store->getMemoryVT() &&
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"Should already have checked that the types match");
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uint64_t Size = Load->getMemoryVT().getStoreSize();
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if (Size > 1 && Size <= 8) {
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// Prefer LHRL, LRL and LGRL.
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if (Load->getBasePtr().getOpcode() == SystemZISD::PCREL_WRAPPER)
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return false;
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// Prefer STHRL, STRL and STGRL.
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if (Store->getBasePtr().getOpcode() == SystemZISD::PCREL_WRAPPER)
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return false;
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}
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// Volatility stops an access from being decomposed.
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if (Load->isVolatile() || Store->isVolatile())
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return false;
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// There's no chance of overlap if the load is invariant.
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if (Load->isInvariant())
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return true;
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// If both operands are aligned, they must be equal or not overlap.
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uint64_t Size = Load->getMemoryVT().getStoreSize();
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if (Load->getAlignment() >= Size && Store->getAlignment() >= Size)
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return true;
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@ -968,6 +968,37 @@ bool SystemZDAGToDAGISel::storeLoadCanUseMVC(SDNode *N) const {
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AliasAnalysis::Location(V2, End2, Store->getTBAAInfo()));
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}
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bool SystemZDAGToDAGISel::storeLoadCanUseMVC(SDNode *N) const {
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StoreSDNode *Store = cast<StoreSDNode>(N);
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LoadSDNode *Load = cast<LoadSDNode>(Store->getValue());
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// Prefer not to use MVC if either address can use ... RELATIVE LONG
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// instructions.
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uint64_t Size = Load->getMemoryVT().getStoreSize();
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if (Size > 1 && Size <= 8) {
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// Prefer LHRL, LRL and LGRL.
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if (Load->getBasePtr().getOpcode() == SystemZISD::PCREL_WRAPPER)
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return false;
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// Prefer STHRL, STRL and STGRL.
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if (Store->getBasePtr().getOpcode() == SystemZISD::PCREL_WRAPPER)
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return false;
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}
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return canUseBlockOperation(Store, Load, AA);
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}
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bool SystemZDAGToDAGISel::storeLoadCanUseBlockBinary(SDNode *N,
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unsigned I) const {
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StoreSDNode *StoreA = cast<StoreSDNode>(N);
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LoadSDNode *LoadA = cast<LoadSDNode>(StoreA->getValue().getOperand(1 - I));
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LoadSDNode *LoadB = cast<LoadSDNode>(StoreA->getValue().getOperand(I));
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if (LoadA->isVolatile() ||
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LoadA->getMemoryVT() != StoreA->getMemoryVT() ||
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LoadA->getBasePtr() != StoreA->getBasePtr())
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return false;
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return canUseBlockOperation(StoreA, LoadB, AA);
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}
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SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
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// Dump information about the Node being selected
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DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
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@ -2054,6 +2054,12 @@ const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
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OPCODE(UDIVREM64);
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OPCODE(MVC);
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OPCODE(MVC_LOOP);
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OPCODE(NC);
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OPCODE(NC_LOOP);
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OPCODE(OC);
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OPCODE(OC_LOOP);
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OPCODE(XC);
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OPCODE(XC_LOOP);
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OPCODE(CLC);
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OPCODE(CLC_LOOP);
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OPCODE(STRCMP);
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@ -3077,6 +3083,15 @@ EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
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case SystemZ::MVCSequence:
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case SystemZ::MVCLoop:
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return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
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case SystemZ::NCSequence:
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case SystemZ::NCLoop:
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return emitMemMemWrapper(MI, MBB, SystemZ::NC);
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case SystemZ::OCSequence:
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case SystemZ::OCLoop:
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return emitMemMemWrapper(MI, MBB, SystemZ::OC);
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case SystemZ::XCSequence:
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case SystemZ::XCLoop:
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return emitMemMemWrapper(MI, MBB, SystemZ::XC);
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case SystemZ::CLCSequence:
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case SystemZ::CLCLoop:
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return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
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@ -93,6 +93,14 @@ namespace SystemZISD {
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// The value of X is passed as an additional operand.
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MVC_LOOP,
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// Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
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NC,
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NC_LOOP,
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OC,
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OC_LOOP,
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XC,
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XC_LOOP,
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// Use CLC to compare two blocks of memory, with the same comments
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// as for MVC and MVC_LOOP.
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CLC,
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@ -86,9 +86,9 @@ def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high),
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def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high),
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(EXTRACT_SUBREG FP128:$src2, subreg_high))>;
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defm LoadStoreF32 : MVCLoadStore<load, store, f32, MVCSequence, 4>;
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defm LoadStoreF64 : MVCLoadStore<load, store, f64, MVCSequence, 8>;
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defm LoadStoreF128 : MVCLoadStore<load, store, f128, MVCSequence, 16>;
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defm LoadStoreF32 : MVCLoadStore<load, f32, MVCSequence, 4>;
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defm LoadStoreF64 : MVCLoadStore<load, f64, MVCSequence, 8>;
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defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>;
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//===----------------------------------------------------------------------===//
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// Load instructions
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@ -350,20 +350,6 @@ let mayLoad = 1, mayStore = 1 in
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let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0W] in
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defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
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defm LoadStore8_32 : MVCLoadStore<anyextloadi8, truncstorei8, i32,
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MVCSequence, 1>;
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defm LoadStore16_32 : MVCLoadStore<anyextloadi16, truncstorei16, i32,
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MVCSequence, 2>;
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defm LoadStore32_32 : MVCLoadStore<load, store, i32, MVCSequence, 4>;
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defm LoadStore8 : MVCLoadStore<anyextloadi8, truncstorei8, i64,
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MVCSequence, 1>;
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defm LoadStore16 : MVCLoadStore<anyextloadi16, truncstorei16, i64,
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MVCSequence, 2>;
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defm LoadStore32 : MVCLoadStore<anyextloadi32, truncstorei32, i64,
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MVCSequence, 4>;
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defm LoadStore64 : MVCLoadStore<load, store, i64, MVCSequence, 8>;
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//===----------------------------------------------------------------------===//
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// Sign extensions
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//===----------------------------------------------------------------------===//
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@ -770,6 +756,10 @@ let Defs = [CC] in {
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// AND to memory
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defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>;
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// Block AND.
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let mayLoad = 1, mayStore = 1 in
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defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>;
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}
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defm : RMWIByte<and, bdaddr12pair, NI>;
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defm : RMWIByte<and, bdaddr20pair, NIY>;
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@ -812,6 +802,10 @@ let Defs = [CC] in {
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// OR to memory
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defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>;
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// Block OR.
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let mayLoad = 1, mayStore = 1 in
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defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>;
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}
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defm : RMWIByte<or, bdaddr12pair, OI>;
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defm : RMWIByte<or, bdaddr20pair, OIY>;
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@ -843,6 +837,10 @@ let Defs = [CC] in {
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// XOR to memory
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defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>;
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// Block XOR.
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let mayLoad = 1, mayStore = 1 in
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defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>;
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}
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defm : RMWIByte<xor, bdaddr12pair, XI>;
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defm : RMWIByte<xor, bdaddr20pair, XIY>;
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@ -1246,3 +1244,19 @@ def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid,
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(i32 63)),
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(i32 63)),
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(Select64 (LGHI -1), (LGHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
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// Peepholes for turning scalar operations into block operations.
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defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
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XCSequence, 1>;
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defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence,
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XCSequence, 2>;
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defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence,
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XCSequence, 4>;
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defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence,
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OCSequence, XCSequence, 1>;
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defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence,
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XCSequence, 2>;
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defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence,
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XCSequence, 4>;
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defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence,
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XCSequence, 8>;
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@ -131,6 +131,18 @@ def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZMemMemLength,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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def z_mvc_loop : SDNode<"SystemZISD::MVC_LOOP", SDT_ZMemMemLoop,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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def z_nc : SDNode<"SystemZISD::NC", SDT_ZMemMemLength,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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def z_nc_loop : SDNode<"SystemZISD::NC_LOOP", SDT_ZMemMemLoop,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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def z_oc : SDNode<"SystemZISD::OC", SDT_ZMemMemLength,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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def z_oc_loop : SDNode<"SystemZISD::OC_LOOP", SDT_ZMemMemLoop,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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def z_xc : SDNode<"SystemZISD::XC", SDT_ZMemMemLength,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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def z_xc_loop : SDNode<"SystemZISD::XC_LOOP", SDT_ZMemMemLoop,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
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def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLength,
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[SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
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def z_clc_loop : SDNode<"SystemZISD::CLC_LOOP", SDT_ZMemMemLoop,
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@ -224,6 +236,31 @@ def nonvolatile_truncstorei8 : NonvolatileStore<truncstorei8>;
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def nonvolatile_truncstorei16 : NonvolatileStore<truncstorei16>;
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def nonvolatile_truncstorei32 : NonvolatileStore<truncstorei32>;
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// A store of a load that can be implemented using MVC.
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def mvc_store : PatFrag<(ops node:$value, node:$addr),
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(unindexedstore node:$value, node:$addr),
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[{ return storeLoadCanUseMVC(N); }]>;
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// Binary read-modify-write operations on memory in which the other
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// operand is also memory and for which block operations like NC can
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// be used. There are two patterns for each operator, depending on
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// which operand contains the "other" load.
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multiclass block_op<SDPatternOperator operator> {
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def "1" : PatFrag<(ops node:$value, node:$addr),
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(unindexedstore (operator node:$value,
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(unindexedload node:$addr)),
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node:$addr),
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[{ return storeLoadCanUseBlockBinary(N, 0); }]>;
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def "2" : PatFrag<(ops node:$value, node:$addr),
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(unindexedstore (operator (unindexedload node:$addr),
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node:$value),
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node:$addr),
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[{ return storeLoadCanUseBlockBinary(N, 1); }]>;
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}
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defm block_and : block_op<and>;
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defm block_or : block_op<or>;
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defm block_xor : block_op<xor>;
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// Insertions.
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def inserti8 : PatFrag<(ops node:$src1, node:$src2),
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(or (and node:$src1, -256), node:$src2)>;
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@ -66,20 +66,39 @@ multiclass InsertMem<string type, Instruction insn, RegisterOperand cls,
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(insn cls:$src1, mode:$src2)>;
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}
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// Use MVC instruction INSN for a load of type LOAD followed by a store
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// of type STORE. VT is the type of the intermediate register and LENGTH
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// is the number of bytes to copy (which may be smaller than VT).
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multiclass MVCLoadStore<SDPatternOperator load, SDPatternOperator store,
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ValueType vt, Instruction insn, bits<5> length> {
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def Pat : PatFrag<(ops node:$dest, node:$src),
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(store (vt (load node:$src)), node:$dest),
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[{ return storeLoadCanUseMVC(N); }]>;
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def : Pat<(!cast<SDPatternOperator>(NAME##"Pat") bdaddr12only:$dest,
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bdaddr12only:$src),
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// Try to use MVC instruction INSN for a load of type LOAD followed by a store
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// of the same size. VT is the type of the intermediate (legalized) value and
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// LENGTH is the number of bytes loaded by LOAD.
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multiclass MVCLoadStore<SDPatternOperator load, ValueType vt, Instruction insn,
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bits<5> length> {
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def : Pat<(mvc_store (vt (load bdaddr12only:$src)), bdaddr12only:$dest),
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(insn bdaddr12only:$dest, bdaddr12only:$src, length)>;
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}
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// Use NC-like instruction INSN for block_op operation OPERATOR.
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// The other operand is a load of type LOAD, which accesses LENGTH bytes.
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// VT is the intermediate legalized type in which the binary operation
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// is actually done.
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multiclass BinaryLoadStore<SDPatternOperator operator, SDPatternOperator load,
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ValueType vt, Instruction insn, bits<5> length> {
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def : Pat<(operator (vt (load bdaddr12only:$src)), bdaddr12only:$dest),
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(insn bdaddr12only:$dest, bdaddr12only:$src, length)>;
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}
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// A convenient way of generating all block peepholes for a particular
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// LOAD/VT/LENGTH combination.
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multiclass BlockLoadStore<SDPatternOperator load, ValueType vt,
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Instruction mvc, Instruction nc, Instruction oc,
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Instruction xc, bits<5> length> {
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defm : MVCLoadStore<load, vt, mvc, length>;
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defm : BinaryLoadStore<block_and1, load, vt, nc, length>;
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defm : BinaryLoadStore<block_and2, load, vt, nc, length>;
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defm : BinaryLoadStore<block_or1, load, vt, oc, length>;
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defm : BinaryLoadStore<block_or2, load, vt, oc, length>;
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defm : BinaryLoadStore<block_xor1, load, vt, xc, length>;
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defm : BinaryLoadStore<block_xor2, load, vt, xc, length>;
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}
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// Record that INSN is a LOAD AND TEST that can be used to compare
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// registers in CLS against zero. The instruction has separate R1 and R2
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// operands, but they must be the same when the instruction is used like this.
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397
test/CodeGen/SystemZ/and-08.ll
Normal file
397
test/CodeGen/SystemZ/and-08.ll
Normal file
@ -0,0 +1,397 @@
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; Test memory-to-memory ANDs.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@g1 = global i8 1
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@g2 = global i16 2
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; Test the simple i8 case.
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define void @f1(i8 *%ptr1) {
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; CHECK-LABEL: f1:
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; CHECK: nc 1(1,%r2), 0(%r2)
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; CHECK: br %r14
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%ptr2 = getelementptr i8 *%ptr1, i64 1
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%val = load i8 *%ptr1
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%old = load i8 *%ptr2
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%and = and i8 %val, %old
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store i8 %and, i8 *%ptr2
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ret void
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}
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; ...and again in reverse.
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define void @f2(i8 *%ptr1) {
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; CHECK-LABEL: f2:
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; CHECK: nc 1(1,%r2), 0(%r2)
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; CHECK: br %r14
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%ptr2 = getelementptr i8 *%ptr1, i64 1
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%val = load i8 *%ptr1
|
||||
%old = load i8 *%ptr2
|
||||
%and = and i8 %old, %val
|
||||
store i8 %and, i8 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test i8 cases where one value is zero-extended to 32 bits and the other
|
||||
; sign-extended.
|
||||
define void @f3(i8 *%ptr1) {
|
||||
; CHECK-LABEL: f3:
|
||||
; CHECK: nc 1(1,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i8 *%ptr1, i64 1
|
||||
%val = load i8 *%ptr1
|
||||
%extval = zext i8 %val to i32
|
||||
%old = load i8 *%ptr2
|
||||
%extold = sext i8 %old to i32
|
||||
%and = and i32 %extval, %extold
|
||||
%trunc = trunc i32 %and to i8
|
||||
store i8 %trunc, i8 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; ...and again with the extension types reversed.
|
||||
define void @f4(i8 *%ptr1) {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK: nc 1(1,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i8 *%ptr1, i64 1
|
||||
%val = load i8 *%ptr1
|
||||
%extval = sext i8 %val to i32
|
||||
%old = load i8 *%ptr2
|
||||
%extold = zext i8 %old to i32
|
||||
%and = and i32 %extval, %extold
|
||||
%trunc = trunc i32 %and to i8
|
||||
store i8 %trunc, i8 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; ...and again with two sign extensions.
|
||||
define void @f5(i8 *%ptr1) {
|
||||
; CHECK-LABEL: f5:
|
||||
; CHECK: nc 1(1,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i8 *%ptr1, i64 1
|
||||
%val = load i8 *%ptr1
|
||||
%extval = sext i8 %val to i32
|
||||
%old = load i8 *%ptr2
|
||||
%extold = sext i8 %old to i32
|
||||
%and = and i32 %extval, %extold
|
||||
%trunc = trunc i32 %and to i8
|
||||
store i8 %trunc, i8 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; ...and again with two zero extensions.
|
||||
define void @f6(i8 *%ptr1) {
|
||||
; CHECK-LABEL: f6:
|
||||
; CHECK: nc 1(1,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i8 *%ptr1, i64 1
|
||||
%val = load i8 *%ptr1
|
||||
%extval = zext i8 %val to i32
|
||||
%old = load i8 *%ptr2
|
||||
%extold = zext i8 %old to i32
|
||||
%and = and i32 %extval, %extold
|
||||
%trunc = trunc i32 %and to i8
|
||||
store i8 %trunc, i8 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test i8 cases where the value is extended to 64 bits (just one case
|
||||
; this time).
|
||||
define void @f7(i8 *%ptr1) {
|
||||
; CHECK-LABEL: f7:
|
||||
; CHECK: nc 1(1,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i8 *%ptr1, i64 1
|
||||
%val = load i8 *%ptr1
|
||||
%extval = sext i8 %val to i64
|
||||
%old = load i8 *%ptr2
|
||||
%extold = zext i8 %old to i64
|
||||
%and = and i64 %extval, %extold
|
||||
%trunc = trunc i64 %and to i8
|
||||
store i8 %trunc, i8 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test the simple i16 case.
|
||||
define void @f8(i16 *%ptr1) {
|
||||
; CHECK-LABEL: f8:
|
||||
; CHECK: nc 2(2,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i16 *%ptr1, i64 1
|
||||
%val = load i16 *%ptr1
|
||||
%old = load i16 *%ptr2
|
||||
%and = and i16 %val, %old
|
||||
store i16 %and, i16 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test i16 cases where the value is extended to 32 bits.
|
||||
define void @f9(i16 *%ptr1) {
|
||||
; CHECK-LABEL: f9:
|
||||
; CHECK: nc 2(2,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i16 *%ptr1, i64 1
|
||||
%val = load i16 *%ptr1
|
||||
%extval = zext i16 %val to i32
|
||||
%old = load i16 *%ptr2
|
||||
%extold = sext i16 %old to i32
|
||||
%and = and i32 %extval, %extold
|
||||
%trunc = trunc i32 %and to i16
|
||||
store i16 %trunc, i16 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test i16 cases where the value is extended to 64 bits.
|
||||
define void @f10(i16 *%ptr1) {
|
||||
; CHECK-LABEL: f10:
|
||||
; CHECK: nc 2(2,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i16 *%ptr1, i64 1
|
||||
%val = load i16 *%ptr1
|
||||
%extval = sext i16 %val to i64
|
||||
%old = load i16 *%ptr2
|
||||
%extold = zext i16 %old to i64
|
||||
%and = and i64 %extval, %extold
|
||||
%trunc = trunc i64 %and to i16
|
||||
store i16 %trunc, i16 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test the simple i32 case.
|
||||
define void @f11(i32 *%ptr1) {
|
||||
; CHECK-LABEL: f11:
|
||||
; CHECK: nc 4(4,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i32 *%ptr1, i64 1
|
||||
%val = load i32 *%ptr1
|
||||
%old = load i32 *%ptr2
|
||||
%and = and i32 %old, %val
|
||||
store i32 %and, i32 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test i32 cases where the value is extended to 64 bits.
|
||||
define void @f12(i32 *%ptr1) {
|
||||
; CHECK-LABEL: f12:
|
||||
; CHECK: nc 4(4,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i32 *%ptr1, i64 1
|
||||
%val = load i32 *%ptr1
|
||||
%extval = sext i32 %val to i64
|
||||
%old = load i32 *%ptr2
|
||||
%extold = zext i32 %old to i64
|
||||
%and = and i64 %extval, %extold
|
||||
%trunc = trunc i64 %and to i32
|
||||
store i32 %trunc, i32 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test the i64 case.
|
||||
define void @f13(i64 *%ptr1) {
|
||||
; CHECK-LABEL: f13:
|
||||
; CHECK: nc 8(8,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i64 *%ptr1, i64 1
|
||||
%val = load i64 *%ptr1
|
||||
%old = load i64 *%ptr2
|
||||
%and = and i64 %old, %val
|
||||
store i64 %and, i64 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Make sure that we don't use NC if the first load is volatile.
|
||||
define void @f14(i64 *%ptr1) {
|
||||
; CHECK-LABEL: f14:
|
||||
; CHECK-NOT: nc
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i64 *%ptr1, i64 1
|
||||
%val = load volatile i64 *%ptr1
|
||||
%old = load i64 *%ptr2
|
||||
%and = and i64 %old, %val
|
||||
store i64 %and, i64 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; ...likewise the second.
|
||||
define void @f15(i64 *%ptr1) {
|
||||
; CHECK-LABEL: f15:
|
||||
; CHECK-NOT: nc
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i64 *%ptr1, i64 1
|
||||
%val = load i64 *%ptr1
|
||||
%old = load volatile i64 *%ptr2
|
||||
%and = and i64 %old, %val
|
||||
store i64 %and, i64 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; ...likewise the store.
|
||||
define void @f16(i64 *%ptr1) {
|
||||
; CHECK-LABEL: f16:
|
||||
; CHECK-NOT: nc
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i64 *%ptr1, i64 1
|
||||
%val = load i64 *%ptr1
|
||||
%old = load i64 *%ptr2
|
||||
%and = and i64 %old, %val
|
||||
store volatile i64 %and, i64 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test that NC is used for aligned loads and stores, even if there is
|
||||
; no way of telling whether they alias.
|
||||
define void @f17(i64 *%ptr1, i64 *%ptr2) {
|
||||
; CHECK-LABEL: f17:
|
||||
; CHECK: nc 0(8,%r3), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%val = load i64 *%ptr1
|
||||
%old = load i64 *%ptr2
|
||||
%and = and i64 %old, %val
|
||||
store i64 %and, i64 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; ...but if one of the loads isn't aligned, we can't be sure.
|
||||
define void @f18(i64 *%ptr1, i64 *%ptr2) {
|
||||
; CHECK-LABEL: f18:
|
||||
; CHECK-NOT: nc
|
||||
; CHECK: br %r14
|
||||
%val = load i64 *%ptr1, align 2
|
||||
%old = load i64 *%ptr2
|
||||
%and = and i64 %old, %val
|
||||
store i64 %and, i64 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Repeat the previous test with the operands in the opposite order.
|
||||
define void @f19(i64 *%ptr1, i64 *%ptr2) {
|
||||
; CHECK-LABEL: f19:
|
||||
; CHECK-NOT: nc
|
||||
; CHECK: br %r14
|
||||
%val = load i64 *%ptr1, align 2
|
||||
%old = load i64 *%ptr2
|
||||
%and = and i64 %val, %old
|
||||
store i64 %and, i64 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; ...and again with the other operand being unaligned.
|
||||
define void @f20(i64 *%ptr1, i64 *%ptr2) {
|
||||
; CHECK-LABEL: f20:
|
||||
; CHECK-NOT: nc
|
||||
; CHECK: br %r14
|
||||
%val = load i64 *%ptr1
|
||||
%old = load i64 *%ptr2, align 2
|
||||
%and = and i64 %val, %old
|
||||
store i64 %and, i64 *%ptr2, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test a case where there is definite overlap.
|
||||
define void @f21(i64 %base) {
|
||||
; CHECK-LABEL: f21:
|
||||
; CHECK-NOT: nc
|
||||
; CHECK: br %r14
|
||||
%add = add i64 %base, 1
|
||||
%ptr1 = inttoptr i64 %base to i64 *
|
||||
%ptr2 = inttoptr i64 %add to i64 *
|
||||
%val = load i64 *%ptr1
|
||||
%old = load i64 *%ptr2, align 1
|
||||
%and = and i64 %old, %val
|
||||
store i64 %and, i64 *%ptr2, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test that we can use NC for global addresses for i8.
|
||||
define void @f22(i8 *%ptr) {
|
||||
; CHECK-LABEL: f22:
|
||||
; CHECK: larl [[REG:%r[0-5]]], g1
|
||||
; CHECK: nc 0(1,%r2), 0([[REG]])
|
||||
; CHECK: br %r14
|
||||
%val = load i8 *@g1
|
||||
%old = load i8 *%ptr
|
||||
%and = and i8 %val, %old
|
||||
store i8 %and, i8 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; ...and again with the global on the store.
|
||||
define void @f23(i8 *%ptr) {
|
||||
; CHECK-LABEL: f23:
|
||||
; CHECK: larl [[REG:%r[0-5]]], g1
|
||||
; CHECK: nc 0(1,[[REG]]), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%val = load i8 *%ptr
|
||||
%old = load i8 *@g1
|
||||
%and = and i8 %val, %old
|
||||
store i8 %and, i8 *@g1
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test that we use NC even where LHRL and STHRL are available.
|
||||
define void @f24(i16 *%ptr) {
|
||||
; CHECK-LABEL: f24:
|
||||
; CHECK: larl [[REG:%r[0-5]]], g2
|
||||
; CHECK: nc 0(2,%r2), 0([[REG]])
|
||||
; CHECK: br %r14
|
||||
%val = load i16 *@g2
|
||||
%old = load i16 *%ptr
|
||||
%and = and i16 %val, %old
|
||||
store i16 %and, i16 *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; ...likewise on the other side.
|
||||
define void @f25(i16 *%ptr) {
|
||||
; CHECK-LABEL: f25:
|
||||
; CHECK: larl [[REG:%r[0-5]]], g2
|
||||
; CHECK: nc 0(2,[[REG]]), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%val = load i16 *%ptr
|
||||
%old = load i16 *@g2
|
||||
%and = and i16 %val, %old
|
||||
store i16 %and, i16 *@g2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test a case where offset disambiguation is enough.
|
||||
define void @f26(i64 *%ptr1) {
|
||||
; CHECK-LABEL: f26:
|
||||
; CHECK: nc 8(8,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i64 *%ptr1, i64 1
|
||||
%val = load i64 *%ptr1, align 1
|
||||
%old = load i64 *%ptr2, align 1
|
||||
%and = and i64 %old, %val
|
||||
store i64 %and, i64 *%ptr2, align 1
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test a case where TBAA tells us there is no alias.
|
||||
define void @f27(i64 *%ptr1, i64 *%ptr2) {
|
||||
; CHECK-LABEL: f27:
|
||||
; CHECK: nc 0(8,%r3), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%val = load i64 *%ptr1, align 2, !tbaa !1
|
||||
%old = load i64 *%ptr2, align 2, !tbaa !2
|
||||
%and = and i64 %old, %val
|
||||
store i64 %and, i64 *%ptr2, align 2, !tbaa !2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test a case where TBAA information is present but doesn't help.
|
||||
define void @f28(i64 *%ptr1, i64 *%ptr2) {
|
||||
; CHECK-LABEL: f28:
|
||||
; CHECK-NOT: nc
|
||||
; CHECK: br %r14
|
||||
%val = load i64 *%ptr1, align 2, !tbaa !1
|
||||
%old = load i64 *%ptr2, align 2, !tbaa !1
|
||||
%and = and i64 %old, %val
|
||||
store i64 %and, i64 *%ptr2, align 2, !tbaa !1
|
||||
ret void
|
||||
}
|
||||
|
||||
!0 = metadata !{ metadata !"root" }
|
||||
!1 = metadata !{ metadata !"set1", metadata !0 }
|
||||
!2 = metadata !{ metadata !"set2", metadata !0 }
|
57
test/CodeGen/SystemZ/or-08.ll
Normal file
57
test/CodeGen/SystemZ/or-08.ll
Normal file
@ -0,0 +1,57 @@
|
||||
; Test memory-to-memory ORs.
|
||||
;
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
; Test the simple i8 case.
|
||||
define void @f1(i8 *%ptr1) {
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK: oc 1(1,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i8 *%ptr1, i64 1
|
||||
%val = load i8 *%ptr1
|
||||
%old = load i8 *%ptr2
|
||||
%or = or i8 %val, %old
|
||||
store i8 %or, i8 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test the simple i16 case.
|
||||
define void @f2(i16 *%ptr1) {
|
||||
; CHECK-LABEL: f2:
|
||||
; CHECK: oc 2(2,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i16 *%ptr1, i64 1
|
||||
%val = load i16 *%ptr1
|
||||
%old = load i16 *%ptr2
|
||||
%or = or i16 %val, %old
|
||||
store i16 %or, i16 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test the simple i32 case.
|
||||
define void @f3(i32 *%ptr1) {
|
||||
; CHECK-LABEL: f3:
|
||||
; CHECK: oc 4(4,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i32 *%ptr1, i64 1
|
||||
%val = load i32 *%ptr1
|
||||
%old = load i32 *%ptr2
|
||||
%or = or i32 %old, %val
|
||||
store i32 %or, i32 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test the i64 case.
|
||||
define void @f4(i64 *%ptr1) {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK: oc 8(8,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i64 *%ptr1, i64 1
|
||||
%val = load i64 *%ptr1
|
||||
%old = load i64 *%ptr2
|
||||
%or = or i64 %old, %val
|
||||
store i64 %or, i64 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Leave other more complicated tests to and-08.ll.
|
57
test/CodeGen/SystemZ/xor-08.ll
Normal file
57
test/CodeGen/SystemZ/xor-08.ll
Normal file
@ -0,0 +1,57 @@
|
||||
; Test memory-to-memory XORs.
|
||||
;
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
||||
|
||||
; Test the simple i8 case.
|
||||
define void @f1(i8 *%ptr1) {
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK: xc 1(1,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i8 *%ptr1, i64 1
|
||||
%val = load i8 *%ptr1
|
||||
%old = load i8 *%ptr2
|
||||
%xor = xor i8 %val, %old
|
||||
store i8 %xor, i8 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test the simple i16 case.
|
||||
define void @f2(i16 *%ptr1) {
|
||||
; CHECK-LABEL: f2:
|
||||
; CHECK: xc 2(2,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i16 *%ptr1, i64 1
|
||||
%val = load i16 *%ptr1
|
||||
%old = load i16 *%ptr2
|
||||
%xor = xor i16 %val, %old
|
||||
store i16 %xor, i16 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test the simple i32 case.
|
||||
define void @f3(i32 *%ptr1) {
|
||||
; CHECK-LABEL: f3:
|
||||
; CHECK: xc 4(4,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i32 *%ptr1, i64 1
|
||||
%val = load i32 *%ptr1
|
||||
%old = load i32 *%ptr2
|
||||
%xor = xor i32 %old, %val
|
||||
store i32 %xor, i32 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test the i64 case.
|
||||
define void @f4(i64 *%ptr1) {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK: xc 8(8,%r2), 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr2 = getelementptr i64 *%ptr1, i64 1
|
||||
%val = load i64 *%ptr1
|
||||
%old = load i64 *%ptr2
|
||||
%xor = xor i64 %old, %val
|
||||
store i64 %xor, i64 *%ptr2
|
||||
ret void
|
||||
}
|
||||
|
||||
; Leave other more complicated tests to and-08.ll.
|
@ -4861,6 +4861,42 @@
|
||||
# CHECK: mxdb %f13, 0
|
||||
0xed 0xd0 0x00 0x00 0x00 0x07
|
||||
|
||||
# CHECK: nc 0(1), 0
|
||||
0xd4 0x00 0x00 0x00 0x00 0x00
|
||||
|
||||
# CHECK: nc 0(1), 0(%r1)
|
||||
0xd4 0x00 0x00 0x00 0x10 0x00
|
||||
|
||||
# CHECK: nc 0(1), 0(%r15)
|
||||
0xd4 0x00 0x00 0x00 0xf0 0x00
|
||||
|
||||
# CHECK: nc 0(1), 4095
|
||||
0xd4 0x00 0x00 0x00 0x0f 0xff
|
||||
|
||||
# CHECK: nc 0(1), 4095(%r1)
|
||||
0xd4 0x00 0x00 0x00 0x1f 0xff
|
||||
|
||||
# CHECK: nc 0(1), 4095(%r15)
|
||||
0xd4 0x00 0x00 0x00 0xff 0xff
|
||||
|
||||
# CHECK: nc 0(1,%r1), 0
|
||||
0xd4 0x00 0x10 0x00 0x00 0x00
|
||||
|
||||
# CHECK: nc 0(1,%r15), 0
|
||||
0xd4 0x00 0xf0 0x00 0x00 0x00
|
||||
|
||||
# CHECK: nc 4095(1,%r1), 0
|
||||
0xd4 0x00 0x1f 0xff 0x00 0x00
|
||||
|
||||
# CHECK: nc 4095(1,%r15), 0
|
||||
0xd4 0x00 0xff 0xff 0x00 0x00
|
||||
|
||||
# CHECK: nc 0(256,%r1), 0
|
||||
0xd4 0xff 0x10 0x00 0x00 0x00
|
||||
|
||||
# CHECK: nc 0(256,%r15), 0
|
||||
0xd4 0xff 0xf0 0x00 0x00 0x00
|
||||
|
||||
# CHECK: ngr %r0, %r0
|
||||
0xb9 0x80 0x00 0x00
|
||||
|
||||
@ -5095,6 +5131,42 @@
|
||||
# CHECK: ny %r15, 0
|
||||
0xe3 0xf0 0x00 0x00 0x00 0x54
|
||||
|
||||
# CHECK: oc 0(1), 0
|
||||
0xd6 0x00 0x00 0x00 0x00 0x00
|
||||
|
||||
# CHECK: oc 0(1), 0(%r1)
|
||||
0xd6 0x00 0x00 0x00 0x10 0x00
|
||||
|
||||
# CHECK: oc 0(1), 0(%r15)
|
||||
0xd6 0x00 0x00 0x00 0xf0 0x00
|
||||
|
||||
# CHECK: oc 0(1), 4095
|
||||
0xd6 0x00 0x00 0x00 0x0f 0xff
|
||||
|
||||
# CHECK: oc 0(1), 4095(%r1)
|
||||
0xd6 0x00 0x00 0x00 0x1f 0xff
|
||||
|
||||
# CHECK: oc 0(1), 4095(%r15)
|
||||
0xd6 0x00 0x00 0x00 0xff 0xff
|
||||
|
||||
# CHECK: oc 0(1,%r1), 0
|
||||
0xd6 0x00 0x10 0x00 0x00 0x00
|
||||
|
||||
# CHECK: oc 0(1,%r15), 0
|
||||
0xd6 0x00 0xf0 0x00 0x00 0x00
|
||||
|
||||
# CHECK: oc 4095(1,%r1), 0
|
||||
0xd6 0x00 0x1f 0xff 0x00 0x00
|
||||
|
||||
# CHECK: oc 4095(1,%r15), 0
|
||||
0xd6 0x00 0xff 0xff 0x00 0x00
|
||||
|
||||
# CHECK: oc 0(256,%r1), 0
|
||||
0xd6 0xff 0x10 0x00 0x00 0x00
|
||||
|
||||
# CHECK: oc 0(256,%r15), 0
|
||||
0xd6 0xff 0xf0 0x00 0x00 0x00
|
||||
|
||||
# CHECK: ogr %r0, %r0
|
||||
0xb9 0x81 0x00 0x00
|
||||
|
||||
@ -7012,6 +7084,42 @@
|
||||
# CHECK: tmll %r15, 0
|
||||
0xa7 0xf1 0x00 0x00
|
||||
|
||||
# CHECK: xc 0(1), 0
|
||||
0xd7 0x00 0x00 0x00 0x00 0x00
|
||||
|
||||
# CHECK: xc 0(1), 0(%r1)
|
||||
0xd7 0x00 0x00 0x00 0x10 0x00
|
||||
|
||||
# CHECK: xc 0(1), 0(%r15)
|
||||
0xd7 0x00 0x00 0x00 0xf0 0x00
|
||||
|
||||
# CHECK: xc 0(1), 4095
|
||||
0xd7 0x00 0x00 0x00 0x0f 0xff
|
||||
|
||||
# CHECK: xc 0(1), 4095(%r1)
|
||||
0xd7 0x00 0x00 0x00 0x1f 0xff
|
||||
|
||||
# CHECK: xc 0(1), 4095(%r15)
|
||||
0xd7 0x00 0x00 0x00 0xff 0xff
|
||||
|
||||
# CHECK: xc 0(1,%r1), 0
|
||||
0xd7 0x00 0x10 0x00 0x00 0x00
|
||||
|
||||
# CHECK: xc 0(1,%r15), 0
|
||||
0xd7 0x00 0xf0 0x00 0x00 0x00
|
||||
|
||||
# CHECK: xc 4095(1,%r1), 0
|
||||
0xd7 0x00 0x1f 0xff 0x00 0x00
|
||||
|
||||
# CHECK: xc 4095(1,%r15), 0
|
||||
0xd7 0x00 0xff 0xff 0x00 0x00
|
||||
|
||||
# CHECK: xc 0(256,%r1), 0
|
||||
0xd7 0xff 0x10 0x00 0x00 0x00
|
||||
|
||||
# CHECK: xc 0(256,%r15), 0
|
||||
0xd7 0xff 0xf0 0x00 0x00 0x00
|
||||
|
||||
# CHECK: xgr %r0, %r0
|
||||
0xb9 0x82 0x00 0x00
|
||||
|
||||
|
@ -2051,6 +2051,50 @@
|
||||
n %r0, -1
|
||||
n %r0, 4096
|
||||
|
||||
#CHECK: error: missing length in address
|
||||
#CHECK: nc 0, 0
|
||||
#CHECK: error: missing length in address
|
||||
#CHECK: nc 0(%r1), 0(%r1)
|
||||
#CHECK: error: invalid use of length addressing
|
||||
#CHECK: nc 0(1,%r1), 0(2,%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: nc 0(0,%r1), 0(%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: nc 0(257,%r1), 0(%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: nc -1(1,%r1), 0(%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: nc 4096(1,%r1), 0(%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: nc 0(1,%r1), -1(%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: nc 0(1,%r1), 4096(%r1)
|
||||
#CHECK: error: %r0 used in an address
|
||||
#CHECK: nc 0(1,%r0), 0(%r1)
|
||||
#CHECK: error: %r0 used in an address
|
||||
#CHECK: nc 0(1,%r1), 0(%r0)
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: nc 0(%r1,%r2), 0(%r1)
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: nc 0(1,%r2), 0(%r1,%r2)
|
||||
#CHECK: error: unknown token in expression
|
||||
#CHECK: nc 0(-), 0
|
||||
|
||||
nc 0, 0
|
||||
nc 0(%r1), 0(%r1)
|
||||
nc 0(1,%r1), 0(2,%r1)
|
||||
nc 0(0,%r1), 0(%r1)
|
||||
nc 0(257,%r1), 0(%r1)
|
||||
nc -1(1,%r1), 0(%r1)
|
||||
nc 4096(1,%r1), 0(%r1)
|
||||
nc 0(1,%r1), -1(%r1)
|
||||
nc 0(1,%r1), 4096(%r1)
|
||||
nc 0(1,%r0), 0(%r1)
|
||||
nc 0(1,%r1), 0(%r0)
|
||||
nc 0(%r1,%r2), 0(%r1)
|
||||
nc 0(1,%r2), 0(%r1,%r2)
|
||||
nc 0(-), 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: ng %r0, -524289
|
||||
#CHECK: error: invalid operand
|
||||
@ -2167,6 +2211,50 @@
|
||||
o %r0, -1
|
||||
o %r0, 4096
|
||||
|
||||
#CHECK: error: missing length in address
|
||||
#CHECK: oc 0, 0
|
||||
#CHECK: error: missing length in address
|
||||
#CHECK: oc 0(%r1), 0(%r1)
|
||||
#CHECK: error: invalid use of length addressing
|
||||
#CHECK: oc 0(1,%r1), 0(2,%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: oc 0(0,%r1), 0(%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: oc 0(257,%r1), 0(%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: oc -1(1,%r1), 0(%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: oc 4096(1,%r1), 0(%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: oc 0(1,%r1), -1(%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: oc 0(1,%r1), 4096(%r1)
|
||||
#CHECK: error: %r0 used in an address
|
||||
#CHECK: oc 0(1,%r0), 0(%r1)
|
||||
#CHECK: error: %r0 used in an address
|
||||
#CHECK: oc 0(1,%r1), 0(%r0)
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: oc 0(%r1,%r2), 0(%r1)
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: oc 0(1,%r2), 0(%r1,%r2)
|
||||
#CHECK: error: unknown token in expression
|
||||
#CHECK: oc 0(-), 0
|
||||
|
||||
oc 0, 0
|
||||
oc 0(%r1), 0(%r1)
|
||||
oc 0(1,%r1), 0(2,%r1)
|
||||
oc 0(0,%r1), 0(%r1)
|
||||
oc 0(257,%r1), 0(%r1)
|
||||
oc -1(1,%r1), 0(%r1)
|
||||
oc 4096(1,%r1), 0(%r1)
|
||||
oc 0(1,%r1), -1(%r1)
|
||||
oc 0(1,%r1), 4096(%r1)
|
||||
oc 0(1,%r0), 0(%r1)
|
||||
oc 0(1,%r1), 0(%r0)
|
||||
oc 0(%r1,%r2), 0(%r1)
|
||||
oc 0(1,%r2), 0(%r1,%r2)
|
||||
oc 0(-), 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: og %r0, -524289
|
||||
#CHECK: error: invalid operand
|
||||
@ -2903,6 +2991,50 @@
|
||||
x %r0, -1
|
||||
x %r0, 4096
|
||||
|
||||
#CHECK: error: missing length in address
|
||||
#CHECK: xc 0, 0
|
||||
#CHECK: error: missing length in address
|
||||
#CHECK: xc 0(%r1), 0(%r1)
|
||||
#CHECK: error: invalid use of length addressing
|
||||
#CHECK: xc 0(1,%r1), 0(2,%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: xc 0(0,%r1), 0(%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: xc 0(257,%r1), 0(%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: xc -1(1,%r1), 0(%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: xc 4096(1,%r1), 0(%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: xc 0(1,%r1), -1(%r1)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: xc 0(1,%r1), 4096(%r1)
|
||||
#CHECK: error: %r0 used in an address
|
||||
#CHECK: xc 0(1,%r0), 0(%r1)
|
||||
#CHECK: error: %r0 used in an address
|
||||
#CHECK: xc 0(1,%r1), 0(%r0)
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: xc 0(%r1,%r2), 0(%r1)
|
||||
#CHECK: error: invalid use of indexed addressing
|
||||
#CHECK: xc 0(1,%r2), 0(%r1,%r2)
|
||||
#CHECK: error: unknown token in expression
|
||||
#CHECK: xc 0(-), 0
|
||||
|
||||
xc 0, 0
|
||||
xc 0(%r1), 0(%r1)
|
||||
xc 0(1,%r1), 0(2,%r1)
|
||||
xc 0(0,%r1), 0(%r1)
|
||||
xc 0(257,%r1), 0(%r1)
|
||||
xc -1(1,%r1), 0(%r1)
|
||||
xc 4096(1,%r1), 0(%r1)
|
||||
xc 0(1,%r1), -1(%r1)
|
||||
xc 0(1,%r1), 4096(%r1)
|
||||
xc 0(1,%r0), 0(%r1)
|
||||
xc 0(1,%r1), 0(%r0)
|
||||
xc 0(%r1,%r2), 0(%r1)
|
||||
xc 0(1,%r2), 0(%r1,%r2)
|
||||
xc 0(-), 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: xg %r0, -524289
|
||||
#CHECK: error: invalid operand
|
||||
|
@ -5774,6 +5774,32 @@
|
||||
n %r0, 4095(%r15,%r1)
|
||||
n %r15, 0
|
||||
|
||||
#CHECK: nc 0(1), 0 # encoding: [0xd4,0x00,0x00,0x00,0x00,0x00]
|
||||
#CHECK: nc 0(1), 0(%r1) # encoding: [0xd4,0x00,0x00,0x00,0x10,0x00]
|
||||
#CHECK: nc 0(1), 0(%r15) # encoding: [0xd4,0x00,0x00,0x00,0xf0,0x00]
|
||||
#CHECK: nc 0(1), 4095 # encoding: [0xd4,0x00,0x00,0x00,0x0f,0xff]
|
||||
#CHECK: nc 0(1), 4095(%r1) # encoding: [0xd4,0x00,0x00,0x00,0x1f,0xff]
|
||||
#CHECK: nc 0(1), 4095(%r15) # encoding: [0xd4,0x00,0x00,0x00,0xff,0xff]
|
||||
#CHECK: nc 0(1,%r1), 0 # encoding: [0xd4,0x00,0x10,0x00,0x00,0x00]
|
||||
#CHECK: nc 0(1,%r15), 0 # encoding: [0xd4,0x00,0xf0,0x00,0x00,0x00]
|
||||
#CHECK: nc 4095(1,%r1), 0 # encoding: [0xd4,0x00,0x1f,0xff,0x00,0x00]
|
||||
#CHECK: nc 4095(1,%r15), 0 # encoding: [0xd4,0x00,0xff,0xff,0x00,0x00]
|
||||
#CHECK: nc 0(256,%r1), 0 # encoding: [0xd4,0xff,0x10,0x00,0x00,0x00]
|
||||
#CHECK: nc 0(256,%r15), 0 # encoding: [0xd4,0xff,0xf0,0x00,0x00,0x00]
|
||||
|
||||
nc 0(1), 0
|
||||
nc 0(1), 0(%r1)
|
||||
nc 0(1), 0(%r15)
|
||||
nc 0(1), 4095
|
||||
nc 0(1), 4095(%r1)
|
||||
nc 0(1), 4095(%r15)
|
||||
nc 0(1,%r1), 0
|
||||
nc 0(1,%r15), 0
|
||||
nc 4095(1,%r1), 0
|
||||
nc 4095(1,%r15), 0
|
||||
nc 0(256,%r1), 0
|
||||
nc 0(256,%r15), 0
|
||||
|
||||
#CHECK: ng %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x80]
|
||||
#CHECK: ng %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x80]
|
||||
#CHECK: ng %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x80]
|
||||
@ -5948,6 +5974,32 @@
|
||||
o %r0, 4095(%r15,%r1)
|
||||
o %r15, 0
|
||||
|
||||
#CHECK: oc 0(1), 0 # encoding: [0xd6,0x00,0x00,0x00,0x00,0x00]
|
||||
#CHECK: oc 0(1), 0(%r1) # encoding: [0xd6,0x00,0x00,0x00,0x10,0x00]
|
||||
#CHECK: oc 0(1), 0(%r15) # encoding: [0xd6,0x00,0x00,0x00,0xf0,0x00]
|
||||
#CHECK: oc 0(1), 4095 # encoding: [0xd6,0x00,0x00,0x00,0x0f,0xff]
|
||||
#CHECK: oc 0(1), 4095(%r1) # encoding: [0xd6,0x00,0x00,0x00,0x1f,0xff]
|
||||
#CHECK: oc 0(1), 4095(%r15) # encoding: [0xd6,0x00,0x00,0x00,0xff,0xff]
|
||||
#CHECK: oc 0(1,%r1), 0 # encoding: [0xd6,0x00,0x10,0x00,0x00,0x00]
|
||||
#CHECK: oc 0(1,%r15), 0 # encoding: [0xd6,0x00,0xf0,0x00,0x00,0x00]
|
||||
#CHECK: oc 4095(1,%r1), 0 # encoding: [0xd6,0x00,0x1f,0xff,0x00,0x00]
|
||||
#CHECK: oc 4095(1,%r15), 0 # encoding: [0xd6,0x00,0xff,0xff,0x00,0x00]
|
||||
#CHECK: oc 0(256,%r1), 0 # encoding: [0xd6,0xff,0x10,0x00,0x00,0x00]
|
||||
#CHECK: oc 0(256,%r15), 0 # encoding: [0xd6,0xff,0xf0,0x00,0x00,0x00]
|
||||
|
||||
oc 0(1), 0
|
||||
oc 0(1), 0(%r1)
|
||||
oc 0(1), 0(%r15)
|
||||
oc 0(1), 4095
|
||||
oc 0(1), 4095(%r1)
|
||||
oc 0(1), 4095(%r15)
|
||||
oc 0(1,%r1), 0
|
||||
oc 0(1,%r15), 0
|
||||
oc 4095(1,%r1), 0
|
||||
oc 4095(1,%r15), 0
|
||||
oc 0(256,%r1), 0
|
||||
oc 0(256,%r15), 0
|
||||
|
||||
#CHECK: og %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x81]
|
||||
#CHECK: og %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x81]
|
||||
#CHECK: og %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x81]
|
||||
@ -7340,6 +7392,32 @@
|
||||
x %r0, 4095(%r15,%r1)
|
||||
x %r15, 0
|
||||
|
||||
#CHECK: xc 0(1), 0 # encoding: [0xd7,0x00,0x00,0x00,0x00,0x00]
|
||||
#CHECK: xc 0(1), 0(%r1) # encoding: [0xd7,0x00,0x00,0x00,0x10,0x00]
|
||||
#CHECK: xc 0(1), 0(%r15) # encoding: [0xd7,0x00,0x00,0x00,0xf0,0x00]
|
||||
#CHECK: xc 0(1), 4095 # encoding: [0xd7,0x00,0x00,0x00,0x0f,0xff]
|
||||
#CHECK: xc 0(1), 4095(%r1) # encoding: [0xd7,0x00,0x00,0x00,0x1f,0xff]
|
||||
#CHECK: xc 0(1), 4095(%r15) # encoding: [0xd7,0x00,0x00,0x00,0xff,0xff]
|
||||
#CHECK: xc 0(1,%r1), 0 # encoding: [0xd7,0x00,0x10,0x00,0x00,0x00]
|
||||
#CHECK: xc 0(1,%r15), 0 # encoding: [0xd7,0x00,0xf0,0x00,0x00,0x00]
|
||||
#CHECK: xc 4095(1,%r1), 0 # encoding: [0xd7,0x00,0x1f,0xff,0x00,0x00]
|
||||
#CHECK: xc 4095(1,%r15), 0 # encoding: [0xd7,0x00,0xff,0xff,0x00,0x00]
|
||||
#CHECK: xc 0(256,%r1), 0 # encoding: [0xd7,0xff,0x10,0x00,0x00,0x00]
|
||||
#CHECK: xc 0(256,%r15), 0 # encoding: [0xd7,0xff,0xf0,0x00,0x00,0x00]
|
||||
|
||||
xc 0(1), 0
|
||||
xc 0(1), 0(%r1)
|
||||
xc 0(1), 0(%r15)
|
||||
xc 0(1), 4095
|
||||
xc 0(1), 4095(%r1)
|
||||
xc 0(1), 4095(%r15)
|
||||
xc 0(1,%r1), 0
|
||||
xc 0(1,%r15), 0
|
||||
xc 4095(1,%r1), 0
|
||||
xc 4095(1,%r15), 0
|
||||
xc 0(256,%r1), 0
|
||||
xc 0(256,%r15), 0
|
||||
|
||||
#CHECK: xg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x82]
|
||||
#CHECK: xg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x82]
|
||||
#CHECK: xg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x82]
|
||||
|
Loading…
x
Reference in New Issue
Block a user