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Revert "Refactor optimizeUncoalescable logic"
Likely broke compilation on ARM: http://lab.llvm.org:8011/builders/clang-native-arm-lnt/builds/13054 This reverts commit 0b7824464fbe3d3f386e2d4aef6a431422709e53. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242311 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
ae1ebf6cf7
commit
162c547bf6
@ -107,8 +107,6 @@ STATISTIC(NumUncoalescableCopies, "Number of uncoalescable copies optimized");
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STATISTIC(NumRewrittenCopies, "Number of copies rewritten");
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namespace {
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class ValueTrackerResult;
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class PeepholeOptimizer : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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@ -173,55 +171,6 @@ namespace {
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}
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};
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/// \brief Helper class to hold a reply for ValueTracker queries. Contains the
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/// returned sources for a given search and the instructions where the sources
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/// were tracked from.
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class ValueTrackerResult {
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private:
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/// Track all sources found by one ValueTracker query.
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SmallVector<TargetInstrInfo::RegSubRegPair, 2> RegSrcs;
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/// Instruction using the sources in 'RegSrcs'.
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const MachineInstr *Inst;
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public:
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ValueTrackerResult() : Inst(nullptr) {}
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ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) {
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addSource(Reg, SubReg);
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}
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bool isValid() const { return getNumSources() > 0; }
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void setInst(const MachineInstr *I) { Inst = I; }
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const MachineInstr *getInst() const { return Inst; }
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void clear() {
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RegSrcs.clear();
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Inst = nullptr;
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}
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void addSource(unsigned SrcReg, unsigned SrcSubReg) {
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RegSrcs.push_back(TargetInstrInfo::RegSubRegPair(SrcReg, SrcSubReg));
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}
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void setSource(int Idx, unsigned SrcReg, unsigned SrcSubReg) {
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assert(Idx < getNumSources() && "Reg pair source out of index");
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RegSrcs[Idx] = TargetInstrInfo::RegSubRegPair(SrcReg, SrcSubReg);
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}
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int getNumSources() const { return RegSrcs.size(); }
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unsigned getSrcReg(int Idx) const {
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assert(Idx < getNumSources() && "Reg source out of index");
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return RegSrcs[Idx].Reg;
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}
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unsigned getSrcSubReg(int Idx) const {
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assert(Idx < getNumSources() && "SubReg source out of index");
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return RegSrcs[Idx].SubReg;
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}
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};
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/// \brief Helper class to track the possible sources of a value defined by
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/// a (chain of) copy related instructions.
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/// Given a definition (instruction and definition index), this class
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@ -264,23 +213,23 @@ namespace {
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/// \brief Dispatcher to the right underlying implementation of
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/// getNextSource.
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ValueTrackerResult getNextSourceImpl();
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bool getNextSourceImpl(unsigned &SrcReg, unsigned &SrcSubReg);
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/// \brief Specialized version of getNextSource for Copy instructions.
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ValueTrackerResult getNextSourceFromCopy();
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bool getNextSourceFromCopy(unsigned &SrcReg, unsigned &SrcSubReg);
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/// \brief Specialized version of getNextSource for Bitcast instructions.
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ValueTrackerResult getNextSourceFromBitcast();
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bool getNextSourceFromBitcast(unsigned &SrcReg, unsigned &SrcSubReg);
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/// \brief Specialized version of getNextSource for RegSequence
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/// instructions.
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ValueTrackerResult getNextSourceFromRegSequence();
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bool getNextSourceFromRegSequence(unsigned &SrcReg, unsigned &SrcSubReg);
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/// \brief Specialized version of getNextSource for InsertSubreg
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/// instructions.
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ValueTrackerResult getNextSourceFromInsertSubreg();
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bool getNextSourceFromInsertSubreg(unsigned &SrcReg, unsigned &SrcSubReg);
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/// \brief Specialized version of getNextSource for ExtractSubreg
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/// instructions.
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ValueTrackerResult getNextSourceFromExtractSubreg();
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bool getNextSourceFromExtractSubreg(unsigned &SrcReg, unsigned &SrcSubReg);
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/// \brief Specialized version of getNextSource for SubregToReg
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/// instructions.
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ValueTrackerResult getNextSourceFromSubregToReg();
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bool getNextSourceFromSubregToReg(unsigned &SrcReg, unsigned &SrcSubReg);
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public:
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/// \brief Create a ValueTracker instance for the value defined by \p Reg.
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@ -327,10 +276,16 @@ namespace {
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/// \brief Following the use-def chain, get the next available source
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/// for the tracked value.
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/// \return A ValueTrackerResult containing the a set of registers
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/// and sub registers with tracked values. A ValueTrackerResult with
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/// an empty set of registers means no source was found.
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ValueTrackerResult getNextSource();
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/// When the returned value is not nullptr, \p SrcReg gives the register
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/// that contain the tracked value.
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/// \note The sub register index returned in \p SrcSubReg must be used
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/// on \p SrcReg to access the actual value.
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/// \return Unless the returned value is nullptr (i.e., no source found),
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/// \p SrcReg gives the register of the next source used in the returned
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/// instruction and \p SrcSubReg the sub-register index to be used on that
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/// source to get the tracked value. When nullptr is returned, no
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/// alternative source has been found.
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const MachineInstr *getNextSource(unsigned &SrcReg, unsigned &SrcSubReg);
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/// \brief Get the last register where the initial value can be found.
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/// Initially this is the register of the definition.
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@ -605,11 +560,11 @@ bool PeepholeOptimizer::findNextSource(unsigned &Reg, unsigned &SubReg) {
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// or find a more suitable source.
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ValueTracker ValTracker(Reg, DefSubReg, *MRI, !DisableAdvCopyOpt, TII);
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do {
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ValueTrackerResult Res = ValTracker.getNextSource();
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if (!Res.isValid())
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unsigned CopySrcReg, CopySrcSubReg;
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if (!ValTracker.getNextSource(CopySrcReg, CopySrcSubReg))
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break;
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Src = Res.getSrcReg(0);
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SrcSubReg = Res.getSrcSubReg(0);
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Src = CopySrcReg;
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SrcSubReg = CopySrcSubReg;
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// Do not extend the live-ranges of physical registers as they add
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// constraints to the register allocator.
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@ -698,7 +653,7 @@ public:
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/// \brief Rewrite the current source with \p NewReg and \p NewSubReg
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/// if possible.
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/// \return True if the rewriting was possible, false otherwise.
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/// \return True if the rewritting was possible, false otherwise.
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virtual bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) {
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if (!CopyLike.isCopy() || CurrentSrcIdx != 1)
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return false;
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@ -707,91 +662,6 @@ public:
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MOSrc.setSubReg(NewSubReg);
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return true;
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}
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/// \brief Rewrite the current source with \p NewSrcReg and \p NewSecSubReg
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/// by creating a new COPY instruction. \p DefReg and \p DefSubReg contain the
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/// definition to be rewritten from the original copylike instruction.
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/// \return The new COPY if the rewriting was possible, nullptr otherwise.
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/// This is needed to handle Uncoalescable copies, since they are copy
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/// like instructions that aren't recognized by the register allocator.
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virtual MachineInstr *RewriteCurrentSource(unsigned DefReg,
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unsigned DefSubReg,
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unsigned NewSrcReg,
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unsigned NewSrcSubReg) {
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return nullptr;
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}
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};
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/// \brief Helper class to rewrite uncoalescable copy like instructions
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/// into new COPY (coalescable friendly) instructions.
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class UncoalescableRewriter : public CopyRewriter {
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protected:
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const TargetInstrInfo &TII;
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MachineRegisterInfo &MRI;
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/// The number of defs in the bitcast
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unsigned NumDefs;
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public:
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UncoalescableRewriter(MachineInstr &MI, const TargetInstrInfo &TII,
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MachineRegisterInfo &MRI)
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: CopyRewriter(MI), TII(TII), MRI(MRI) {
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NumDefs = MI.getDesc().getNumDefs();
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}
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/// \brief Get the next rewritable def source (TrackReg, TrackSubReg)
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/// All such sources need to be considered rewritable in order to
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/// rewrite a uncoalescable copy-like instruction. This method return
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/// each definition that must be checked if rewritable.
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///
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bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
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unsigned &TrackReg,
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unsigned &TrackSubReg) override {
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// Find the next non-dead definition and continue from there.
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if (CurrentSrcIdx == NumDefs)
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return false;
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while (CopyLike.getOperand(CurrentSrcIdx).isDead()) {
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++CurrentSrcIdx;
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if (CurrentSrcIdx == NumDefs)
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return false;
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}
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// What we track are the alternative sources of the definition.
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const MachineOperand &MODef = CopyLike.getOperand(CurrentSrcIdx);
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TrackReg = MODef.getReg();
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TrackSubReg = MODef.getSubReg();
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CurrentSrcIdx++;
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return true;
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}
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/// \brief Rewrite the current source with \p NewSrcReg and \p NewSrcSubReg
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/// by creating a new COPY instruction. \p DefReg and \p DefSubReg contain the
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/// definition to be rewritten from the original copylike instruction.
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/// \return The new COPY if the rewriting was possible, nullptr otherwise.
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MachineInstr *RewriteCurrentSource(unsigned DefReg, unsigned DefSubReg,
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unsigned NewSrcReg,
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unsigned NewSrcSubReg) override {
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assert(!TargetRegisterInfo::isPhysicalRegister(DefReg) &&
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"We do not rewrite physical registers");
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const TargetRegisterClass *DefRC = MRI.getRegClass(DefReg);
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unsigned NewVR = MRI.createVirtualRegister(DefRC);
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MachineInstr *NewCopy =
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BuildMI(*CopyLike.getParent(), &CopyLike, CopyLike.getDebugLoc(),
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TII.get(TargetOpcode::COPY), NewVR)
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.addReg(NewSrcReg, 0, NewSrcSubReg);
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NewCopy->getOperand(0).setSubReg(DefSubReg);
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if (DefSubReg)
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NewCopy->getOperand(0).setIsUndef();
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MRI.replaceRegWith(DefReg, NewVR);
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MRI.clearKillFlags(NewVR);
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return NewCopy;
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}
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};
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/// \brief Specialized rewriter for INSERT_SUBREG instruction.
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@ -980,13 +850,7 @@ public:
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/// \return A pointer to a dynamically allocated CopyRewriter or nullptr
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/// if no rewriter works for \p MI.
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static CopyRewriter *getCopyRewriter(MachineInstr &MI,
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const TargetInstrInfo &TII,
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MachineRegisterInfo &MRI) {
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// Handle uncoalescable copy-like instructions.
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if (MI.isBitcast() || (MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
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MI.isExtractSubregLike()))
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return new UncoalescableRewriter(MI, TII, MRI);
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const TargetInstrInfo &TII) {
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switch (MI.getOpcode()) {
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default:
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return nullptr;
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@ -1025,7 +889,7 @@ bool PeepholeOptimizer::optimizeCoalescableCopy(MachineInstr *MI) {
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bool Changed = false;
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// Get the right rewriter for the current copy.
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std::unique_ptr<CopyRewriter> CpyRewriter(getCopyRewriter(*MI, *TII, *MRI));
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std::unique_ptr<CopyRewriter> CpyRewriter(getCopyRewriter(*MI, *TII));
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// If none exists, bails out.
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if (!CpyRewriter)
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return false;
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@ -1035,8 +899,9 @@ bool PeepholeOptimizer::optimizeCoalescableCopy(MachineInstr *MI) {
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TrackSubReg)) {
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unsigned NewSrc = TrackReg;
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unsigned NewSubReg = TrackSubReg;
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// Try to find a more suitable source. If we failed to do so, or get the
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// actual source, move to the next source.
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// Try to find a more suitable source.
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// If we failed to do so, or get the actual source,
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// move to the next source.
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if (!findNextSource(NewSrc, NewSubReg) || SrcReg == NewSrc)
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continue;
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// Rewrite source.
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@ -1074,47 +939,45 @@ bool PeepholeOptimizer::optimizeUncoalescableCopy(
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SmallVector<
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std::pair<TargetInstrInfo::RegSubRegPair, TargetInstrInfo::RegSubRegPair>,
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4> RewritePairs;
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// Get the right rewriter for the current copy.
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std::unique_ptr<CopyRewriter> CpyRewriter(getCopyRewriter(*MI, *TII, *MRI));
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// If none exists, bails out.
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if (!CpyRewriter)
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return false;
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for (const MachineOperand &MODef : MI->defs()) {
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if (MODef.isDead())
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// We can ignore those.
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continue;
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// Rewrite each rewritable source by generating new COPYs. This works
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// differently from optimizeCoalescableCopy since it first makes sure that all
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// definitions can be rewritten.
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unsigned SrcReg, SrcSubReg, TrackReg, TrackSubReg;
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while (CpyRewriter->getNextRewritableSource(SrcReg, SrcSubReg, TrackReg,
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TrackSubReg)) {
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// If a physical register is here, this is probably for a good reason.
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// Do not rewrite that.
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if (TargetRegisterInfo::isPhysicalRegister(TrackReg))
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if (TargetRegisterInfo::isPhysicalRegister(MODef.getReg()))
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return false;
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// If we do not know how to rewrite this definition, there is no point
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// in trying to kill this instruction.
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TargetInstrInfo::RegSubRegPair Def(TrackReg, TrackSubReg);
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TargetInstrInfo::RegSubRegPair Def(MODef.getReg(), MODef.getSubReg());
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TargetInstrInfo::RegSubRegPair Src = Def;
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if (!findNextSource(Src.Reg, Src.SubReg))
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return false;
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RewritePairs.push_back(std::make_pair(Def, Src));
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}
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// The change is possible for all defs, do it.
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for (const auto &PairDefSrc : RewritePairs) {
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const auto &Def = PairDefSrc.first;
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const auto &Src = PairDefSrc.second;
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// Rewrite the "copy" in a way the register coalescer understands.
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MachineInstr *NewCopy = CpyRewriter->RewriteCurrentSource(
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Def.Reg, Def.SubReg, Src.Reg, Src.SubReg);
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assert(NewCopy && "Should be able to always generate a new copy");
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// We extended the lifetime of Src and clear the kill flags to
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// account for that.
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MRI->clearKillFlags(Src.Reg);
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assert(!TargetRegisterInfo::isPhysicalRegister(Def.Reg) &&
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"We do not rewrite physical registers");
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const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
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unsigned NewVR = MRI->createVirtualRegister(DefRC);
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MachineInstr *NewCopy = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
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TII->get(TargetOpcode::COPY),
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NewVR).addReg(Src.Reg, 0, Src.SubReg);
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NewCopy->getOperand(0).setSubReg(Def.SubReg);
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if (Def.SubReg)
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NewCopy->getOperand(0).setIsUndef();
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LocalMIs.insert(NewCopy);
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MRI->replaceRegWith(Def.Reg, NewVR);
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MRI->clearKillFlags(NewVR);
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// We extended the lifetime of Src.
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// Clear the kill flags to account for that.
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MRI->clearKillFlags(Src.Reg);
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}
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// MI is now dead.
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MI->eraseFromParent();
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@ -1327,7 +1190,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
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return Changed;
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}
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ValueTrackerResult ValueTracker::getNextSourceFromCopy() {
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bool ValueTracker::getNextSourceFromCopy(unsigned &SrcReg,
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unsigned &SrcSubReg) {
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assert(Def->isCopy() && "Invalid definition");
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// Copy instruction are supposed to be: Def = Src.
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// If someone breaks this assumption, bad things will happen everywhere.
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@ -1336,26 +1200,29 @@ ValueTrackerResult ValueTracker::getNextSourceFromCopy() {
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if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
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// If we look for a different subreg, it means we want a subreg of src.
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// Bails as we do not support composing subreg yet.
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return ValueTrackerResult();
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return false;
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// Otherwise, we want the whole source.
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const MachineOperand &Src = Def->getOperand(1);
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return ValueTrackerResult(Src.getReg(), Src.getSubReg());
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SrcReg = Src.getReg();
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SrcSubReg = Src.getSubReg();
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return true;
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}
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ValueTrackerResult ValueTracker::getNextSourceFromBitcast() {
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bool ValueTracker::getNextSourceFromBitcast(unsigned &SrcReg,
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unsigned &SrcSubReg) {
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assert(Def->isBitcast() && "Invalid definition");
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// Bail if there are effects that a plain copy will not expose.
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if (Def->hasUnmodeledSideEffects())
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return ValueTrackerResult();
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return false;
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// Bitcasts with more than one def are not supported.
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if (Def->getDesc().getNumDefs() != 1)
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return ValueTrackerResult();
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return false;
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if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
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// If we look for a different subreg, it means we want a subreg of the src.
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// Bails as we do not support composing subreg yet.
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return ValueTrackerResult();
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return false;
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unsigned SrcIdx = Def->getNumOperands();
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for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx;
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@ -1366,14 +1233,17 @@ ValueTrackerResult ValueTracker::getNextSourceFromBitcast() {
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assert(!MO.isDef() && "We should have skipped all the definitions by now");
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if (SrcIdx != EndOpIdx)
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// Multiple sources?
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return ValueTrackerResult();
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return false;
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SrcIdx = OpIdx;
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}
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const MachineOperand &Src = Def->getOperand(SrcIdx);
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return ValueTrackerResult(Src.getReg(), Src.getSubReg());
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SrcReg = Src.getReg();
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SrcSubReg = Src.getSubReg();
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return true;
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}
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ValueTrackerResult ValueTracker::getNextSourceFromRegSequence() {
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bool ValueTracker::getNextSourceFromRegSequence(unsigned &SrcReg,
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unsigned &SrcSubReg) {
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assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
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"Invalid definition");
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@ -1392,16 +1262,16 @@ ValueTrackerResult ValueTracker::getNextSourceFromRegSequence() {
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// have this case.
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// If we can ascertain (or force) that this never happens, we could
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// turn that into an assertion.
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return ValueTrackerResult();
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return false;
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if (!TII)
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// We could handle the REG_SEQUENCE here, but we do not want to
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// duplicate the code from the generic TII.
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return ValueTrackerResult();
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return false;
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SmallVector<TargetInstrInfo::RegSubRegPairAndIdx, 8> RegSeqInputRegs;
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if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
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return ValueTrackerResult();
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return false;
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// We are looking at:
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||||
// Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
|
||||
@ -1410,19 +1280,22 @@ ValueTrackerResult ValueTracker::getNextSourceFromRegSequence() {
|
||||
if (RegSeqInput.SubIdx == DefSubReg) {
|
||||
if (RegSeqInput.SubReg)
|
||||
// Bails if we have to compose sub registers.
|
||||
return ValueTrackerResult();
|
||||
return false;
|
||||
|
||||
return ValueTrackerResult(RegSeqInput.Reg, RegSeqInput.SubReg);
|
||||
SrcReg = RegSeqInput.Reg;
|
||||
SrcSubReg = RegSeqInput.SubReg;
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
// If the subreg we are tracking is super-defined by another subreg,
|
||||
// we could follow this value. However, this would require to compose
|
||||
// the subreg and we do not do that for now.
|
||||
return ValueTrackerResult();
|
||||
return false;
|
||||
}
|
||||
|
||||
ValueTrackerResult ValueTracker::getNextSourceFromInsertSubreg() {
|
||||
bool ValueTracker::getNextSourceFromInsertSubreg(unsigned &SrcReg,
|
||||
unsigned &SrcSubReg) {
|
||||
assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) &&
|
||||
"Invalid definition");
|
||||
|
||||
@ -1430,17 +1303,17 @@ ValueTrackerResult ValueTracker::getNextSourceFromInsertSubreg() {
|
||||
// If we are composing subreg, bails out.
|
||||
// Same remark as getNextSourceFromRegSequence.
|
||||
// I.e., this may be turned into an assert.
|
||||
return ValueTrackerResult();
|
||||
return false;
|
||||
|
||||
if (!TII)
|
||||
// We could handle the REG_SEQUENCE here, but we do not want to
|
||||
// duplicate the code from the generic TII.
|
||||
return ValueTrackerResult();
|
||||
return false;
|
||||
|
||||
TargetInstrInfo::RegSubRegPair BaseReg;
|
||||
TargetInstrInfo::RegSubRegPairAndIdx InsertedReg;
|
||||
if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
|
||||
return ValueTrackerResult();
|
||||
return false;
|
||||
|
||||
// We are looking at:
|
||||
// Def = INSERT_SUBREG v0, v1, sub1
|
||||
@ -1450,7 +1323,9 @@ ValueTrackerResult ValueTracker::getNextSourceFromInsertSubreg() {
|
||||
|
||||
// #1 Check if the inserted register matches the required sub index.
|
||||
if (InsertedReg.SubIdx == DefSubReg) {
|
||||
return ValueTrackerResult(InsertedReg.Reg, InsertedReg.SubReg);
|
||||
SrcReg = InsertedReg.Reg;
|
||||
SrcSubReg = InsertedReg.SubReg;
|
||||
return true;
|
||||
}
|
||||
// #2 Otherwise, if the sub register we are looking for is not partial
|
||||
// defined by the inserted element, we can look through the main
|
||||
@ -1461,7 +1336,7 @@ ValueTrackerResult ValueTracker::getNextSourceFromInsertSubreg() {
|
||||
// subregisters, bails out.
|
||||
if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) ||
|
||||
BaseReg.SubReg)
|
||||
return ValueTrackerResult();
|
||||
return false;
|
||||
|
||||
// Get the TRI and check if the inserted sub-register overlaps with the
|
||||
// sub-register we are tracking.
|
||||
@ -1469,13 +1344,16 @@ ValueTrackerResult ValueTracker::getNextSourceFromInsertSubreg() {
|
||||
if (!TRI ||
|
||||
(TRI->getSubRegIndexLaneMask(DefSubReg) &
|
||||
TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)) != 0)
|
||||
return ValueTrackerResult();
|
||||
return false;
|
||||
// At this point, the value is available in v0 via the same subreg
|
||||
// we used for Def.
|
||||
return ValueTrackerResult(BaseReg.Reg, DefSubReg);
|
||||
SrcReg = BaseReg.Reg;
|
||||
SrcSubReg = DefSubReg;
|
||||
return true;
|
||||
}
|
||||
|
||||
ValueTrackerResult ValueTracker::getNextSourceFromExtractSubreg() {
|
||||
bool ValueTracker::getNextSourceFromExtractSubreg(unsigned &SrcReg,
|
||||
unsigned &SrcSubReg) {
|
||||
assert((Def->isExtractSubreg() ||
|
||||
Def->isExtractSubregLike()) && "Invalid definition");
|
||||
// We are looking at:
|
||||
@ -1484,26 +1362,29 @@ ValueTrackerResult ValueTracker::getNextSourceFromExtractSubreg() {
|
||||
// Bails if we have to compose sub registers.
|
||||
// Indeed, if DefSubReg != 0, we would have to compose it with sub0.
|
||||
if (DefSubReg)
|
||||
return ValueTrackerResult();
|
||||
return false;
|
||||
|
||||
if (!TII)
|
||||
// We could handle the EXTRACT_SUBREG here, but we do not want to
|
||||
// duplicate the code from the generic TII.
|
||||
return ValueTrackerResult();
|
||||
return false;
|
||||
|
||||
TargetInstrInfo::RegSubRegPairAndIdx ExtractSubregInputReg;
|
||||
if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
|
||||
return ValueTrackerResult();
|
||||
return false;
|
||||
|
||||
// Bails if we have to compose sub registers.
|
||||
// Likewise, if v0.subreg != 0, we would have to compose v0.subreg with sub0.
|
||||
if (ExtractSubregInputReg.SubReg)
|
||||
return ValueTrackerResult();
|
||||
return false;
|
||||
// Otherwise, the value is available in the v0.sub0.
|
||||
return ValueTrackerResult(ExtractSubregInputReg.Reg, ExtractSubregInputReg.SubIdx);
|
||||
SrcReg = ExtractSubregInputReg.Reg;
|
||||
SrcSubReg = ExtractSubregInputReg.SubIdx;
|
||||
return true;
|
||||
}
|
||||
|
||||
ValueTrackerResult ValueTracker::getNextSourceFromSubregToReg() {
|
||||
bool ValueTracker::getNextSourceFromSubregToReg(unsigned &SrcReg,
|
||||
unsigned &SrcSubReg) {
|
||||
assert(Def->isSubregToReg() && "Invalid definition");
|
||||
// We are looking at:
|
||||
// Def = SUBREG_TO_REG Imm, v0, sub0
|
||||
@ -1513,71 +1394,71 @@ ValueTrackerResult ValueTracker::getNextSourceFromSubregToReg() {
|
||||
// we track are included in sub0 and if yes, we would have to
|
||||
// determine the right subreg in v0.
|
||||
if (DefSubReg != Def->getOperand(3).getImm())
|
||||
return ValueTrackerResult();
|
||||
return false;
|
||||
// Bails if we have to compose sub registers.
|
||||
// Likewise, if v0.subreg != 0, we would have to compose it with sub0.
|
||||
if (Def->getOperand(2).getSubReg())
|
||||
return ValueTrackerResult();
|
||||
return false;
|
||||
|
||||
return ValueTrackerResult(Def->getOperand(2).getReg(),
|
||||
Def->getOperand(3).getImm());
|
||||
SrcReg = Def->getOperand(2).getReg();
|
||||
SrcSubReg = Def->getOperand(3).getImm();
|
||||
return true;
|
||||
}
|
||||
|
||||
ValueTrackerResult ValueTracker::getNextSourceImpl() {
|
||||
bool ValueTracker::getNextSourceImpl(unsigned &SrcReg, unsigned &SrcSubReg) {
|
||||
assert(Def && "This method needs a valid definition");
|
||||
|
||||
assert(
|
||||
(DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic()) &&
|
||||
Def->getOperand(DefIdx).isDef() && "Invalid DefIdx");
|
||||
if (Def->isCopy())
|
||||
return getNextSourceFromCopy();
|
||||
return getNextSourceFromCopy(SrcReg, SrcSubReg);
|
||||
if (Def->isBitcast())
|
||||
return getNextSourceFromBitcast();
|
||||
return getNextSourceFromBitcast(SrcReg, SrcSubReg);
|
||||
// All the remaining cases involve "complex" instructions.
|
||||
// Bails if we did not ask for the advanced tracking.
|
||||
if (!UseAdvancedTracking)
|
||||
return ValueTrackerResult();
|
||||
return false;
|
||||
if (Def->isRegSequence() || Def->isRegSequenceLike())
|
||||
return getNextSourceFromRegSequence();
|
||||
return getNextSourceFromRegSequence(SrcReg, SrcSubReg);
|
||||
if (Def->isInsertSubreg() || Def->isInsertSubregLike())
|
||||
return getNextSourceFromInsertSubreg();
|
||||
return getNextSourceFromInsertSubreg(SrcReg, SrcSubReg);
|
||||
if (Def->isExtractSubreg() || Def->isExtractSubregLike())
|
||||
return getNextSourceFromExtractSubreg();
|
||||
return getNextSourceFromExtractSubreg(SrcReg, SrcSubReg);
|
||||
if (Def->isSubregToReg())
|
||||
return getNextSourceFromSubregToReg();
|
||||
return ValueTrackerResult();
|
||||
return getNextSourceFromSubregToReg(SrcReg, SrcSubReg);
|
||||
return false;
|
||||
}
|
||||
|
||||
ValueTrackerResult ValueTracker::getNextSource() {
|
||||
const MachineInstr *ValueTracker::getNextSource(unsigned &SrcReg,
|
||||
unsigned &SrcSubReg) {
|
||||
// If we reach a point where we cannot move up in the use-def chain,
|
||||
// there is nothing we can get.
|
||||
if (!Def)
|
||||
return ValueTrackerResult();
|
||||
return nullptr;
|
||||
|
||||
ValueTrackerResult Res = getNextSourceImpl();
|
||||
if (Res.isValid()) {
|
||||
const MachineInstr *PrevDef = nullptr;
|
||||
// Try to find the next source.
|
||||
if (getNextSourceImpl(SrcReg, SrcSubReg)) {
|
||||
// Update definition, definition index, and subregister for the
|
||||
// next call of getNextSource.
|
||||
// Update the current register.
|
||||
bool OneRegSrc = Res.getNumSources() == 1;
|
||||
if (OneRegSrc)
|
||||
Reg = Res.getSrcReg(0);
|
||||
// Update the result before moving up in the use-def chain
|
||||
// with the instruction containing the last found sources.
|
||||
Res.setInst(Def);
|
||||
|
||||
Reg = SrcReg;
|
||||
// Update the return value before moving up in the use-def chain.
|
||||
PrevDef = Def;
|
||||
// If we can still move up in the use-def chain, move to the next
|
||||
// defintion.
|
||||
if (!TargetRegisterInfo::isPhysicalRegister(Reg) && OneRegSrc) {
|
||||
if (!TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
||||
Def = MRI.getVRegDef(Reg);
|
||||
DefIdx = MRI.def_begin(Reg).getOperandNo();
|
||||
DefSubReg = Res.getSrcSubReg(0);
|
||||
return Res;
|
||||
DefSubReg = SrcSubReg;
|
||||
return PrevDef;
|
||||
}
|
||||
}
|
||||
// If we end up here, this means we will not be able to find another source
|
||||
// for the next iteration. Make sure any new call to getNextSource bails out
|
||||
// early by cutting the use-def chain.
|
||||
// for the next iteration.
|
||||
// Make sure any new call to getNextSource bails out early by cutting the
|
||||
// use-def chain.
|
||||
Def = nullptr;
|
||||
return Res;
|
||||
return PrevDef;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user