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R600/SI: Refactor VOP3 instruction definitions

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213571 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2014-07-21 17:44:29 +00:00
parent 3ee2c33655
commit 163d8ce61f
2 changed files with 52 additions and 21 deletions
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2
lib/Target/R600/SIInstrFormats.td
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@ -57,6 +57,8 @@ class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
let hasSideEffects = 0; let hasSideEffects = 0;
let UseNamedOperandTable = 1; let UseNamedOperandTable = 1;
let VOP3 = 1; let VOP3 = 1;
int Size = 8;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

71
lib/Target/R600/SIInstrInfo.td
View File

@ -284,18 +284,56 @@ class SIMCInstr <string pseudo, int subtarget> {
int Subtarget = subtarget; int Subtarget = subtarget;
} }
class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
VOP3Common <outs, ins, "", pattern>,
VOP <opName>,
SIMCInstr<opName, SISubtarget.NONE> {
let isPseudo = 1;
}
class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
VOP3 <op, outs, ins, asm, []>,
SIMCInstr<opName, SISubtarget.SI>;
multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern, multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
string opName> { string opName> {
def "" : VOP3Common <outs, ins, "", pattern>, VOP <opName>, def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
SIMCInstr<OpName, SISubtarget.NONE> {
let isPseudo = 1;
}
def _si : VOP3 <op, outs, ins, asm, []>, SIMCInstr<opName, SISubtarget.SI>; def _si : VOP3_Real_si <op, outs, ins, asm, opName>;
} }
multiclass VOP3_1_m <bits<8> op, dag outs, dag ins, string asm,
list<dag> pattern, string opName> {
def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
let src1 = 0, src1_modifiers = 0, src2 = 0, src2_modifiers = 0 in {
def _si : VOP3_Real_si <
{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
outs, ins, asm, opName
>;
} // src1 = 0, src1_modifiers = 0, src2 = 0, src2_modifiers = 0
}
multiclass VOP3_2_m <bits<6> op, dag outs, dag ins, string asm,
list<dag> pattern, string opName, string revOp> {
def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
let src2 = 0, src2_modifiers = 0 in {
def _si : VOP3_Real_si <
{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
outs, ins, asm, opName>,
VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
} // src2 = 0, src2_modifiers = 0
}
// This must always be right before the operand being input modified. // This must always be right before the operand being input modified.
def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> { def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
let PrintMethod = "printOperandAndMods"; let PrintMethod = "printOperandAndMods";
@ -309,17 +347,11 @@ multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
opName#"_e32 $dst, $src0", pattern opName#"_e32 $dst, $src0", pattern
>, VOP <opName>; >, VOP <opName>;
def _e64 : VOP3 < defm _e64 : VOP3_1_m <
{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, op,
(outs drc:$dst), (outs drc:$dst),
(ins InputMods:$src0_modifiers, src:$src0, i32imm:$clamp, i32imm:$omod), (ins InputMods:$src0_modifiers, src:$src0, i32imm:$clamp, i32imm:$omod),
opName#"_e64 $dst, $src0_modifiers, $clamp, $omod", [] opName#"_e64 $dst, $src0_modifiers, $clamp, $omod", [], opName>;
>, VOP <opName> {
let src1 = 0;
let src1_modifiers = 0;
let src2 = 0;
let src2_modifiers = 0;
}
} }
multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern>
@ -341,17 +373,14 @@ multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
opName#"_e32 $dst, $src0, $src1", pattern opName#"_e32 $dst, $src0, $src1", pattern
>, VOP <opName>, VOP2_REV<revOp#"_e32", !eq(revOp, opName)>; >, VOP <opName>, VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
def _e64 : VOP3 < defm _e64 : VOP3_2_m <
{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, op,
(outs vrc:$dst), (outs vrc:$dst),
(ins InputMods:$src0_modifiers, arc:$src0, (ins InputMods:$src0_modifiers, arc:$src0,
InputMods:$src1_modifiers, arc:$src1, InputMods:$src1_modifiers, arc:$src1,
i32imm:$clamp, i32imm:$omod), i32imm:$clamp, i32imm:$omod),
opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod", [] opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod", [],
>, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> { opName, revOp>;
let src2 = 0;
let src2_modifiers = 0;
}
} }
multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern, multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern,