6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand

Browse Source 
does not have a legal type.  The legalizer does not know how to handle those
nodes.  Radar 7854640.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101282 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-04-14 20:45:23 +00:00
parent ce931088f3
commit 164cd8b8d3
2 changed files with 32 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -2167,6 +2167,13 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
SDValue Op = N->getOperand(0); SDValue Op = N->getOperand(0);
// Do not create a VMOVDRR or VMOVRRD node if the operand type is not
// legal. The legalizer won't know what to do with that.
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (!TLI.isTypeLegal(Op.getValueType()))
return SDValue();
DebugLoc dl = N->getDebugLoc(); DebugLoc dl = N->getDebugLoc();
if (N->getValueType(0) == MVT::f64) { if (N->getValueType(0) == MVT::f64) {
// Turn i64->f64 into VMOVDRR. // Turn i64->f64 into VMOVDRR.
@ -3114,21 +3121,21 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
void ARMTargetLowering::ReplaceNodeResults(SDNode *N, void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) { SelectionDAG &DAG) {
SDValue Res;
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
llvm_unreachable("Don't know how to custom expand this!"); llvm_unreachable("Don't know how to custom expand this!");
return; break;
case ISD::BIT_CONVERT: case ISD::BIT_CONVERT:
Results.push_back(ExpandBIT_CONVERT(N, DAG)); Res = ExpandBIT_CONVERT(N, DAG);
return; break;
case ISD::SRL: case ISD::SRL:
case ISD::SRA: { case ISD::SRA:
SDValue Res = LowerShift(N, DAG, Subtarget); Res = LowerShift(N, DAG, Subtarget);
if (Res.getNode()) break;
Results.push_back(Res);
return;
}
} }
if (Res.getNode())
Results.push_back(Res);
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

16
test/CodeGen/ARM/2010-04-14-SplitVector.ll Normal file
View File

@ -0,0 +1,16 @@
; RUN: llc < %s -march=arm -mcpu=arm1136jf-s
; Radar 7854640
define arm_apcscc void @test() nounwind {
bb:
br i1 undef, label %bb9, label %bb10
bb9:
%tmp63 = bitcast <4 x float> zeroinitializer to i128
%tmp64 = trunc i128 %tmp63 to i32
br label %bb10
bb10:
%0 = phi i32 [ %tmp64, %bb9 ], [ undef, %bb ]
ret void
}