From 1655be290cf871f22b1da1fc700ad9e1deab2a01 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Sun, 12 Jan 2014 04:13:17 +0000 Subject: [PATCH] The SPARCv9 ABI returns a float in %f0. This is different from the argument passing convention which puts the first float argument in %f1. With this patch, all returned floats are treated as if the 'inreg' flag were set. This means multiple float return values get packed in %f0, %f1, %f2, ... Note that when returning a struct in registers, clang will set the 'inreg' flag on the return value, so that behavior is unchanged. This also happens when returning a float _Complex. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199028 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Sparc/SparcCallingConv.td | 11 ++++++++++- lib/Target/Sparc/SparcISelLowering.cpp | 4 ++-- test/CodeGen/SPARC/64abi.ll | 8 ++++---- test/CodeGen/SPARC/64cond.ll | 2 +- test/CodeGen/SPARC/constpool.ll | 6 +++--- 5 files changed, 20 insertions(+), 11 deletions(-) diff --git a/lib/Target/Sparc/SparcCallingConv.td b/lib/Target/Sparc/SparcCallingConv.td index acd4ec21de4..dfaaabf344a 100644 --- a/lib/Target/Sparc/SparcCallingConv.td +++ b/lib/Target/Sparc/SparcCallingConv.td @@ -103,7 +103,7 @@ def RetCC_Sparc32 : CallingConv<[ // Function return values are passed exactly like function arguments, except a // struct up to 32 bytes in size can be returned in registers. -// Function arguments AND return values. +// Function arguments AND most return values. def CC_Sparc64 : CallingConv<[ // The frontend uses the inreg flag to indicate i32 and float arguments from // structs. These arguments are not promoted to 64 bits, but they can still @@ -118,6 +118,15 @@ def CC_Sparc64 : CallingConv<[ CCCustom<"CC_Sparc64_Full"> ]>; +def RetCC_Sparc64 : CallingConv<[ + // A single f32 return value always goes in %f0. The ABI doesn't specify what + // happens to multiple f32 return values outside a struct. + CCIfType<[f32], CCCustom<"CC_Sparc64_Half">>, + + // Otherwise, return values are passed exactly like arguments. + CCDelegateTo +]>; + // Callee-saved registers are handled by the register window mechanism. def CSR : CalleeSavedRegs<(add)> { let OtherPreserved = (add (sequence "I%u", 0, 7), diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 2fce971edf5..fce2c0d5b03 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -254,7 +254,7 @@ SparcTargetLowering::LowerReturn_64(SDValue Chain, DAG.getTarget(), RVLocs, *DAG.getContext()); // Analyze return values. - CCInfo.AnalyzeReturn(Outs, CC_Sparc64); + CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64); SDValue Flag; SmallVector RetOps(1, Chain); @@ -1258,7 +1258,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == 0) CLI.Ins[0].Flags.setInReg(); - RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64); + RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64); // Copy all of the result registers out of their specified physreg. for (unsigned i = 0; i != RVLocs.size(); ++i) { diff --git a/test/CodeGen/SPARC/64abi.ll b/test/CodeGen/SPARC/64abi.ll index 7f9d216e52e..37718889cb7 100644 --- a/test/CodeGen/SPARC/64abi.ll +++ b/test/CodeGen/SPARC/64abi.ll @@ -180,7 +180,7 @@ define void @call_inreg_fi(i32* %p, i32 %i1, float %f5) { } ; CHECK: inreg_ff -; CHECK: fsubs %f0, %f1, %f1 +; CHECK: fsubs %f0, %f1, %f0 define float @inreg_ff(float inreg %a0, ; %f0 float inreg %a1) { ; %f1 %rv = fsub float %a0, %a1 @@ -262,10 +262,10 @@ define void @call_ret_i64_pair(i64* %i0) { ret void } -; This is not a C struct, each member uses 8 bytes. +; This is not a C struct, the i32 member uses 8 bytes, but the float only 4. ; CHECK: ret_i32_float_pair ; CHECK: ld [%i2], %i0 -; CHECK: ld [%i3], %f3 +; CHECK: ld [%i3], %f2 define { i32, float } @ret_i32_float_pair(i32 %a0, i32 %a1, i32* %p, float* %q) { %r1 = load i32* %p @@ -279,7 +279,7 @@ define { i32, float } @ret_i32_float_pair(i32 %a0, i32 %a1, ; CHECK: call_ret_i32_float_pair ; CHECK: call ret_i32_float_pair ; CHECK: st %o0, [%i0] -; CHECK: st %f3, [%i1] +; CHECK: st %f2, [%i1] define void @call_ret_i32_float_pair(i32* %i0, float* %i1) { %rv = call { i32, float } @ret_i32_float_pair(i32 undef, i32 undef, i32* undef, float* undef) diff --git a/test/CodeGen/SPARC/64cond.ll b/test/CodeGen/SPARC/64cond.ll index 8c3f644382d..1bd17a43187 100644 --- a/test/CodeGen/SPARC/64cond.ll +++ b/test/CodeGen/SPARC/64cond.ll @@ -80,7 +80,7 @@ entry: ; CHECK: selectf32_xcc ; CHECK: cmp %i0, %i1 ; CHECK: fmovsg %xcc, %f5, %f7 -; CHECK: fmovs %f7, %f1 +; CHECK: fmovs %f7, %f0 define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) { entry: %tobool = icmp sgt i64 %x, %y diff --git a/test/CodeGen/SPARC/constpool.ll b/test/CodeGen/SPARC/constpool.ll index ea4582b640c..8b0d1d9656d 100644 --- a/test/CodeGen/SPARC/constpool.ll +++ b/test/CodeGen/SPARC/constpool.ll @@ -21,7 +21,7 @@ entry: ; abs44: add %[[R1]], %m44(.LCPI0_0), %[[R2:[gilo][0-7]]] ; abs44: sllx %[[R2]], 12, %[[R3:[gilo][0-7]]] ; abs44: retl -; abs44: ld [%[[R3]]+%l44(.LCPI0_0)], %f1 +; abs44: ld [%[[R3]]+%l44(.LCPI0_0)], %f0 ; abs64: floatCP @@ -31,7 +31,7 @@ entry: ; abs64: add %[[R3]], %hm(.LCPI0_0), %[[R4:[gilo][0-7]]] ; abs64: sllx %[[R4]], 32, %[[R5:[gilo][0-7]]] ; abs64: retl -; abs64: ld [%[[R5]]+%[[R2]]], %f1 +; abs64: ld [%[[R5]]+%[[R2]]], %f0 ; v8pic32: floatCP @@ -50,7 +50,7 @@ entry: ; v9pic32: sethi %hi(.LCPI0_0), %[[R1:[gilo][0-7]]] ; v9pic32: add %[[R1]], %lo(.LCPI0_0), %[[Goffs:[gilo][0-7]]] ; v9pic32: ldx [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]] -; v9pic32: ld [%[[Gaddr]]], %f1 +; v9pic32: ld [%[[Gaddr]]], %f0 ; v9pic32: ret ; v9pic32: restore