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ARM simplify the postidx_reg operand encoding.

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The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-05 16:11:38 +00:00
parent ca8c70b953
commit 16578b5088
4 changed files with 14 additions and 11 deletions
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9
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -1093,8 +1093,7 @@ void ARMOperand::print(raw_ostream &OS) const {
OS << ">";
break;
case PostIndexRegister:
OS << "post-idx register "
<< getAddrOpcStr(ARM_AM::getAM3Op(PostIdxReg.Imm))
OS << "post-idx register " << (PostIdxReg.Imm ? "" : "-")
<< PostIdxReg.RegNum
<< ">";
break;
@ -1872,14 +1871,14 @@ parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
AsmToken Tok = Parser.getTok();
SMLoc S = Tok.getLoc();
bool haveEaten = false;
unsigned Imm = ARM_AM::getAM3Opc(ARM_AM::add, 0);
bool isAdd = true;
int Reg = -1;
if (Tok.is(AsmToken::Plus)) {
Parser.Lex(); // Eat the '+' token.
haveEaten = true;
} else if (Tok.is(AsmToken::Minus)) {
Parser.Lex(); // Eat the '-' token.
Imm = ARM_AM::getAM3Opc(ARM_AM::sub, 0);
isAdd = false;
haveEaten = true;
}
if (Parser.getTok().is(AsmToken::Identifier))
@ -1892,7 +1891,7 @@ parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
}
SMLoc E = Parser.getTok().getLoc();
Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, Imm, S, E));
Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, S, E));
return MatchOperand_Success;
}

10
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -1543,10 +1543,16 @@ static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
++OpIdx;
} else {
// Disassemble the offset reg (Rm).
unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRm(insn))));
MI.addOperand(MCOperand::CreateImm(Offset));
// FIXME: Remove the 'else' once done w/ addrmode3 refactor.
if (Opcode == ARM::STRHTr || Opcode == ARM::LDRSBTr ||
Opcode == ARM::LDRHTr || Opcode == ARM::LDRSHTr)
MI.addOperand(MCOperand::CreateImm(getUBit(insn)));
else {
unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
MI.addOperand(MCOperand::CreateImm(Offset));
}
OpIdx += 2;
}

3
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
View File

@ -387,8 +387,7 @@ void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
const MCOperand &MO1 = MI->getOperand(OpNum);
const MCOperand &MO2 = MI->getOperand(OpNum+1);
O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
<< getRegisterName(MO1.getReg());
O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
}
void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,

3
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
View File

@ -812,8 +812,7 @@ getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
// {3-0} Rm
const MCOperand &MO = MI.getOperand(OpIdx);
const MCOperand &MO1 = MI.getOperand(OpIdx+1);
unsigned Imm = MO1.getImm();
bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
bool isAdd = MO1.getImm() != 0;
return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4);
}