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[AArch64] Prefer UZP for concat_vector of illegal truncs.
Follow-up to r232459: prefer a UZP shuffle to the intermediate truncs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232871 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -7187,8 +7187,9 @@ static SDValue performConcatVectorsCombine(SDNode *N,
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// (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
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// (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
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// (v2i16 (truncate (v2i64)))))
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// (v2i16 (truncate (v2i64)))))
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// ->
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// ->
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// (v4i16 (truncate (v4i32 (concat_vectors (v2i32 (truncate (v2i64))),
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// (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
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// (v2i32 (truncate (v2i64)))))))
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// (v4i32 (bitcast (v2i64))),
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// <0, 2, 4, 6>)))
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// This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
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// This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
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// on both input and result type, so we might generate worse code.
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// on both input and result type, so we might generate worse code.
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// On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
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// On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
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@ -7202,20 +7203,15 @@ static SDValue performConcatVectorsCombine(SDNode *N,
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if (N00VT == N10.getValueType() &&
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if (N00VT == N10.getValueType() &&
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(N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
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(N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
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N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
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N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
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MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v2i32 : MVT::v4i16);
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MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
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#if defined(__GNUC__)
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SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
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#if __GNUC__ == 4 && __GNUC_MINOR__ == 7 && __GNUC_PATCHLEVEL__ == 2
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for (size_t i = 0; i < Mask.size(); ++i)
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// FIXME: g++-4.7.2 might miscompile PerformDAGCombine().
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Mask[i] = i * 2;
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asm volatile("":::"memory");
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return DAG.getNode(ISD::TRUNCATE, dl, VT,
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#endif
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DAG.getVectorShuffle(
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#endif
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MidVT, dl,
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MVT ConcatMidVT = MVT::getVectorVT(MidVT.getVectorElementType(),
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DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
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MidVT.getVectorNumElements() * 2);
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DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
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return DAG.getNode(
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ISD::TRUNCATE, dl, VT,
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DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatMidVT,
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DAG.getNode(ISD::TRUNCATE, dl, MidVT, N00),
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DAG.getNode(ISD::TRUNCATE, dl, MidVT, N10)));
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}
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}
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}
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}
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@ -5,9 +5,8 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define <4 x i16> @test_concat_truncate_v2i64_to_v4i16(<2 x i64> %a, <2 x i64> %b) #0 {
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define <4 x i16> @test_concat_truncate_v2i64_to_v4i16(<2 x i64> %a, <2 x i64> %b) #0 {
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entry:
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entry:
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; CHECK-LABEL: test_concat_truncate_v2i64_to_v4i16:
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; CHECK-LABEL: test_concat_truncate_v2i64_to_v4i16:
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; CHECK-NEXT: xtn.2s v0, v0
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; CHECK-NEXT: uzp1.4s v0, v0, v1
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; CHECK-NEXT: xtn2.4s v0, v1
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; CHECK-NEXT: xtn.4h v0, v0
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; CHECK-NEXT: xtn.4h v0, v0
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; CHECK-NEXT: ret
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; CHECK-NEXT: ret
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%at = trunc <2 x i64> %a to <2 x i16>
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%at = trunc <2 x i64> %a to <2 x i16>
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%bt = trunc <2 x i64> %b to <2 x i16>
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%bt = trunc <2 x i64> %b to <2 x i16>
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@ -18,9 +17,8 @@ entry:
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define <8 x i8> @test_concat_truncate_v4i32_to_v8i8(<4 x i32> %a, <4 x i32> %b) #0 {
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define <8 x i8> @test_concat_truncate_v4i32_to_v8i8(<4 x i32> %a, <4 x i32> %b) #0 {
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entry:
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entry:
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; CHECK-LABEL: test_concat_truncate_v4i32_to_v8i8:
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; CHECK-LABEL: test_concat_truncate_v4i32_to_v8i8:
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; CHECK-NEXT: xtn.4h v0, v0
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; CHECK-NEXT: uzp1.8h v0, v0, v1
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; CHECK-NEXT: xtn2.8h v0, v1
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; CHECK-NEXT: xtn.8b v0, v0
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; CHECK-NEXT: xtn.8b v0, v0
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; CHECK-NEXT: ret
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; CHECK-NEXT: ret
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%at = trunc <4 x i32> %a to <4 x i8>
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%at = trunc <4 x i32> %a to <4 x i8>
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%bt = trunc <4 x i32> %b to <4 x i8>
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%bt = trunc <4 x i32> %b to <4 x i8>
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@ -28,4 +26,16 @@ entry:
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ret <8 x i8> %shuffle
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ret <8 x i8> %shuffle
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}
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}
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define <8 x i16> @test_concat_truncate_v4i32_to_v8i16(<4 x i32> %a, <4 x i32> %b) #0 {
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entry:
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; CHECK-LABEL: test_concat_truncate_v4i32_to_v8i16:
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; CHECK-NEXT: xtn.4h v0, v0
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; CHECK-NEXT: xtn2.8h v0, v1
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; CHECK-NEXT: ret
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%at = trunc <4 x i32> %a to <4 x i16>
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%bt = trunc <4 x i32> %b to <4 x i16>
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%shuffle = shufflevector <4 x i16> %at, <4 x i16> %bt, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %shuffle
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}
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attributes #0 = { nounwind }
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attributes #0 = { nounwind }
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