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[AArch64] Prefer UZP for concat_vector of illegal truncs.

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Follow-up to r232459: prefer a UZP shuffle to the intermediate truncs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232871 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha 2015-03-21 01:08:39 +00:00
parent e3f2e6fcfe
commit 165bd1733b
2 changed files with 28 additions and 22 deletions
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28
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -7187,8 +7187,9 @@ static SDValue performConcatVectorsCombine(SDNode *N,
// (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
// (v2i16 (truncate (v2i64)))))
// ->
// (v4i16 (truncate (v4i32 (concat_vectors (v2i32 (truncate (v2i64))),
// (v2i32 (truncate (v2i64)))))))
// (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
// (v4i32 (bitcast (v2i64))),
// <0, 2, 4, 6>)))
// This isn't really target-specific, but ISD::TRUNCATE legality isn't keyed
// on both input and result type, so we might generate worse code.
// On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8.
@ -7202,20 +7203,15 @@ static SDValue performConcatVectorsCombine(SDNode *N,
if (N00VT == N10.getValueType() &&
(N00VT == MVT::v2i64 || N00VT == MVT::v4i32) &&
N00VT.getScalarSizeInBits() == 4 * VT.getScalarSizeInBits()) {
MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v2i32 : MVT::v4i16);
#if defined(__GNUC__)
#if __GNUC__ == 4 && __GNUC_MINOR__ == 7 && __GNUC_PATCHLEVEL__ == 2
// FIXME: g++-4.7.2 might miscompile PerformDAGCombine().
asm volatile("":::"memory");
#endif
#endif
MVT ConcatMidVT = MVT::getVectorVT(MidVT.getVectorElementType(),
MidVT.getVectorNumElements() * 2);
return DAG.getNode(
ISD::TRUNCATE, dl, VT,
DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatMidVT,
DAG.getNode(ISD::TRUNCATE, dl, MidVT, N00),
DAG.getNode(ISD::TRUNCATE, dl, MidVT, N10)));
MVT MidVT = (N00VT == MVT::v2i64 ? MVT::v4i32 : MVT::v8i16);
SmallVector<int, 8> Mask(MidVT.getVectorNumElements());
for (size_t i = 0; i < Mask.size(); ++i)
Mask[i] = i * 2;
return DAG.getNode(ISD::TRUNCATE, dl, VT,
DAG.getVectorShuffle(
MidVT, dl,
DAG.getNode(ISD::BITCAST, dl, MidVT, N00),
DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));
}
}

18
test/CodeGen/AArch64/concat_vector-truncate-combine.ll
View File

@ -5,8 +5,7 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define <4 x i16> @test_concat_truncate_v2i64_to_v4i16(<2 x i64> %a, <2 x i64> %b) #0 {
entry:
; CHECK-LABEL: test_concat_truncate_v2i64_to_v4i16:
; CHECK-NEXT: xtn.2s v0, v0
; CHECK-NEXT: xtn2.4s v0, v1
; CHECK-NEXT: uzp1.4s v0, v0, v1
; CHECK-NEXT: xtn.4h v0, v0
; CHECK-NEXT: ret
%at = trunc <2 x i64> %a to <2 x i16>
@ -18,8 +17,7 @@ entry:
define <8 x i8> @test_concat_truncate_v4i32_to_v8i8(<4 x i32> %a, <4 x i32> %b) #0 {
entry:
; CHECK-LABEL: test_concat_truncate_v4i32_to_v8i8:
; CHECK-NEXT: xtn.4h v0, v0
; CHECK-NEXT: xtn2.8h v0, v1
; CHECK-NEXT: uzp1.8h v0, v0, v1
; CHECK-NEXT: xtn.8b v0, v0
; CHECK-NEXT: ret
%at = trunc <4 x i32> %a to <4 x i8>
@ -28,4 +26,16 @@ entry:
ret <8 x i8> %shuffle
}
define <8 x i16> @test_concat_truncate_v4i32_to_v8i16(<4 x i32> %a, <4 x i32> %b) #0 {
entry:
; CHECK-LABEL: test_concat_truncate_v4i32_to_v8i16:
; CHECK-NEXT: xtn.4h v0, v0
; CHECK-NEXT: xtn2.8h v0, v1
; CHECK-NEXT: ret
%at = trunc <4 x i32> %a to <4 x i16>
%bt = trunc <4 x i32> %b to <4 x i16>
%shuffle = shufflevector <4 x i16> %at, <4 x i16> %bt, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i16> %shuffle
}
attributes #0 = { nounwind }