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Assign ordering to SDNodes in PromoteNode. Also fixing a subtle bug where BSWAP
was using "Tmp1" in the first getNode call instead of Node->getOperand(0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91936 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2931,22 +2931,29 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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void SelectionDAGLegalize::PromoteNode(SDNode *Node,
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SmallVectorImpl<SDValue> &Results) {
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EVT OVT = Node->getValueType(0);
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if (Node->getOpcode() == ISD::UINT_TO_FP ||
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Node->getOpcode() == ISD::SINT_TO_FP ||
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Node->getOpcode() == ISD::SETCC) {
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Node->getOpcode() == ISD::SETCC)
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OVT = Node->getOperand(0).getValueType();
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}
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EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
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DebugLoc dl = Node->getDebugLoc();
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unsigned Order = DAG.GetOrdering(Node);
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SDValue Tmp1, Tmp2, Tmp3;
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switch (Node->getOpcode()) {
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case ISD::CTTZ:
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case ISD::CTLZ:
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case ISD::CTPOP:
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// Zero extend the argument.
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Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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// Perform the larger operation.
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Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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if (Node->getOpcode() == ISD::CTTZ) {
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//if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
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Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
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@ -2954,21 +2961,37 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node,
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ISD::SETEQ);
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Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
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DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Tmp2.getNode(), Order);
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}
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} else if (Node->getOpcode() == ISD::CTLZ) {
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// Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
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Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
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DAG.getConstant(NVT.getSizeInBits() -
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OVT.getSizeInBits(), NVT));
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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}
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Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
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Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1);
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Results.push_back(Tmp3);
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if (DisableScheduling) DAG.AssignOrdering(Tmp3.getNode(), Order);
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break;
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case ISD::BSWAP: {
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unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
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Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
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Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
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Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
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DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
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Results.push_back(Tmp1);
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Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
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Tmp2 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
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Tmp3 = DAG.getNode(ISD::SRL, dl, NVT, Tmp2,
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DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
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Results.push_back(Tmp3);
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Tmp2.getNode(), Order);
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DAG.AssignOrdering(Tmp3.getNode(), Order);
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}
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break;
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}
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case ISD::FP_TO_UINT:
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@ -2976,12 +2999,14 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node,
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Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
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Node->getOpcode() == ISD::FP_TO_SINT, dl);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::UINT_TO_FP:
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case ISD::SINT_TO_FP:
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Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
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Node->getOpcode() == ISD::SINT_TO_FP, dl);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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case ISD::AND:
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case ISD::OR:
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@ -2996,12 +3021,23 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node,
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} else {
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llvm_report_error("Cannot promote logic operation");
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}
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// Promote each of the values to the new type.
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Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
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Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
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// Perform the larger operation, then convert back
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Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
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Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
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Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Tmp2.getNode(), Order);
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DAG.AssignOrdering(Tmp3.getNode(), Order);
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}
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Tmp1 = DAG.getNode(TruncOp, dl, OVT, Tmp3);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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}
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case ISD::SELECT: {
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@ -3016,18 +3052,34 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node,
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ExtOp = ISD::FP_EXTEND;
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TruncOp = ISD::FP_ROUND;
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}
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Tmp1 = Node->getOperand(0);
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// Promote each of the values to the new type.
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Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
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Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp2.getNode(), Order);
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DAG.AssignOrdering(Tmp3.getNode(), Order);
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}
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// Perform the larger operation, then round down.
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Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
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if (TruncOp != ISD::FP_ROUND)
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Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
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Tmp2 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
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else
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Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
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Tmp2 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
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DAG.getIntPtrConstant(0));
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Results.push_back(Tmp1);
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Results.push_back(Tmp2);
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Tmp2.getNode(), Order);
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}
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break;
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}
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case ISD::VECTOR_SHUFFLE: {
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@ -3039,9 +3091,17 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node,
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Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
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// Convert the shuffle mask to the right # elements.
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Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
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Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1);
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Tmp3 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Tmp2.getNode(), Order);
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DAG.AssignOrdering(Tmp3.getNode(), Order);
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}
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Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp3);
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Results.push_back(Tmp1);
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if (DisableScheduling) DAG.AssignOrdering(Tmp1.getNode(), Order);
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break;
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}
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case ISD::SETCC: {
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@ -3051,10 +3111,17 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node,
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cast<CondCodeSDNode>(Node->getOperand(2))->get();
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ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
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}
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Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
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Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
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Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
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Tmp1, Tmp2, Node->getOperand(2)));
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if (DisableScheduling) {
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DAG.AssignOrdering(Tmp1.getNode(), Order);
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DAG.AssignOrdering(Tmp2.getNode(), Order);
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}
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break;
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}
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}
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@ -648,6 +648,7 @@ SDValue SelectionDAGBuilder::getControlRoot() {
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PendingExports.size());
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PendingExports.clear();
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DAG.setRoot(Root);
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if (DisableScheduling) DAG.AssignOrdering(Root.getNode(), SDNodeOrder);
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return Root;
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}
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