From 1684d47d8f73250616bfbed63607121fb82555bb Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Wed, 22 Jan 2014 21:55:40 +0000 Subject: [PATCH] R600: Add wavefront size property to the subtargets v2 v2: - Initialize wavefront size to 0 reviewed-by: Vincent Lejeune git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199838 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/AMDGPU.td | 12 +++++++++++- lib/Target/R600/AMDGPUSubtarget.cpp | 5 +++++ lib/Target/R600/AMDGPUSubtarget.h | 2 ++ lib/Target/R600/Processors.td | 26 +++++++++++++++----------- 4 files changed, 33 insertions(+), 12 deletions(-) diff --git a/lib/Target/R600/AMDGPU.td b/lib/Target/R600/AMDGPU.td index 36c41560915..c4e5efc8d6e 100644 --- a/lib/Target/R600/AMDGPU.td +++ b/lib/Target/R600/AMDGPU.td @@ -72,6 +72,16 @@ class SubtargetFeatureFetchLimit : def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">; def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">; +class SubtargetFeatureWavefrontSize : SubtargetFeature< + "wavefrontsize"#Value, + "WavefrontSize", + !cast(Value), + "The number of threads per wavefront">; + +def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>; +def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>; +def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>; + class SubtargetFeatureGeneration Implies> : SubtargetFeature ; def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS", - [FeatureFetchLimit16]>; + [FeatureFetchLimit16, FeatureWavefrontSize64]>; def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS", [Feature64BitPtr, FeatureFP64]>; diff --git a/lib/Target/R600/AMDGPUSubtarget.cpp b/lib/Target/R600/AMDGPUSubtarget.cpp index 51d9eadbafe..ed7742cdc2a 100644 --- a/lib/Target/R600/AMDGPUSubtarget.cpp +++ b/lib/Target/R600/AMDGPUSubtarget.cpp @@ -38,6 +38,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) : CaymanISA = false; EnableIRStructurizer = true; EnableIfCvt = true; + WavefrontSize = 0; ParseSubtargetFeatures(GPU, FS); DevName = GPU; } @@ -74,6 +75,10 @@ bool AMDGPUSubtarget::isIfCvtEnabled() const { return EnableIfCvt; } +unsigned +AMDGPUSubtarget::getWavefrontSize() const { + return WavefrontSize; +} bool AMDGPUSubtarget::isTargetELF() const { return false; diff --git a/lib/Target/R600/AMDGPUSubtarget.h b/lib/Target/R600/AMDGPUSubtarget.h index 060571e26b9..53c7d2531a0 100644 --- a/lib/Target/R600/AMDGPUSubtarget.h +++ b/lib/Target/R600/AMDGPUSubtarget.h @@ -51,6 +51,7 @@ private: bool CaymanISA; bool EnableIRStructurizer; bool EnableIfCvt; + unsigned WavefrontSize; InstrItineraryData InstrItins; @@ -68,6 +69,7 @@ public: bool hasCaymanISA() const; bool IsIRStructurizerEnabled() const; bool isIfCvtEnabled() const; + unsigned getWavefrontSize() const; virtual bool enableMachineScheduler() const { return getGeneration() <= NORTHERN_ISLANDS; diff --git a/lib/Target/R600/Processors.td b/lib/Target/R600/Processors.td index 5499a20dfc0..e601f353163 100644 --- a/lib/Target/R600/Processors.td +++ b/lib/Target/R600/Processors.td @@ -17,45 +17,49 @@ def : Proc<"", R600_VLIW5_Itin, [FeatureR600, FeatureVertexCache]>; def : Proc<"r600", R600_VLIW5_Itin, - [FeatureR600 , FeatureVertexCache]>; + [FeatureR600 , FeatureVertexCache, FeatureWavefrontSize64]>; + +def : Proc<"r630", R600_VLIW5_Itin, + [FeatureR600, FeatureVertexCache, FeatureWavefrontSize32]>; def : Proc<"rs880", R600_VLIW5_Itin, - [FeatureR600]>; + [FeatureR600, FeatureWavefrontSize16]>; def : Proc<"rv670", R600_VLIW5_Itin, - [FeatureR600, FeatureFP64, FeatureVertexCache]>; + [FeatureR600, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>; //===----------------------------------------------------------------------===// // R700 //===----------------------------------------------------------------------===// def : Proc<"rv710", R600_VLIW5_Itin, - [FeatureR700, FeatureVertexCache]>; + [FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>; def : Proc<"rv730", R600_VLIW5_Itin, - [FeatureR700, FeatureVertexCache]>; + [FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>; def : Proc<"rv770", R600_VLIW5_Itin, - [FeatureR700, FeatureFP64, FeatureVertexCache]>; + [FeatureR700, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>; //===----------------------------------------------------------------------===// // Evergreen //===----------------------------------------------------------------------===// def : Proc<"cedar", R600_VLIW5_Itin, - [FeatureEvergreen, FeatureVertexCache]>; + [FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize32]>; def : Proc<"redwood", R600_VLIW5_Itin, - [FeatureEvergreen, FeatureVertexCache]>; + [FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64]>; def : Proc<"sumo", R600_VLIW5_Itin, - [FeatureEvergreen]>; + [FeatureEvergreen, FeatureWavefrontSize64]>; def : Proc<"juniper", R600_VLIW5_Itin, - [FeatureEvergreen, FeatureVertexCache]>; + [FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64]>; def : Proc<"cypress", R600_VLIW5_Itin, - [FeatureEvergreen, FeatureFP64, FeatureVertexCache]>; + [FeatureEvergreen, FeatureFP64, FeatureVertexCache, + FeatureWavefrontSize64]>; //===----------------------------------------------------------------------===// // Northern Islands