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Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2011-07-13 23:22:26 +00:00
parent efe2a6557d
commit 16884415db
11 changed files with 230 additions and 249 deletions
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20
lib/Target/ARM/ARMBaseInstrInfo.cpp
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@@ -529,35 +529,23 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
const MachineFunction *MF = MBB.getParent();
const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
// Basic size info comes from the TSFlags field.
const MCInstrDesc &MCID = MI->getDesc();
uint64_t TSFlags = MCID.TSFlags;
if (MCID.getSize())
return MCID.getSize();
unsigned Opc = MI->getOpcode();
switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
default: {
// If this machine instr is an inline asm, measure it.
if (MI->getOpcode() == ARM::INLINEASM)
return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
if (MI->isLabel())
return 0;
unsigned Opc = MI->getOpcode();
switch (Opc) {
default:
llvm_unreachable("Unknown or unset size field for instr!");
case TargetOpcode::IMPLICIT_DEF:
case TargetOpcode::KILL:
case TargetOpcode::PROLOG_LABEL:
case TargetOpcode::EH_LABEL:
case TargetOpcode::DBG_VALUE:
return 0;
}
break;
}
case ARMII::Size8Bytes: return 8; // ARM instruction x 2.
case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
case ARMII::SizeSpecial: {
switch (Opc) {
case ARM::MOVi16_ga_pcrel:
case ARM::MOVTi16_ga_pcrel:
case ARM::t2MOVi16_ga_pcrel:
@@ -621,8 +609,6 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
// Otherwise, pseudo-instruction sizes are zero.
return 0;
}
}
}
return 0; // Not reached
}