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Change codegen for setcc to read the bit directly out of the condition

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register.  Added support in the .td file for the g5-specific variant
  of cr -> gpr moves that executes faster, but we currently don't
  generate it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21314 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-04-18 02:43:24 +00:00
parent d91ff7cd3b
commit 16ac709c63
3 changed files with 36 additions and 45 deletions
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73
lib/Target/PowerPC/PPCISelPattern.cpp
View File

@ -727,6 +727,22 @@ static unsigned getCRIdxForSetCC(unsigned Condition, bool& Inv) {
return 0;
}
/// getCRIdxForBCC - Return the index of the condition register field
/// associated with the PowerPC branch instruction, and whether or not the field
/// is treated as inverted. That is, lt = 0; ge = 0 inverted.
static unsigned getCRIdxForBCC(unsigned Condition, bool& Inv) {
switch (Condition) {
default: assert(0 && "Unknown condition!"); abort();
case PPC::BLT: Inv = false; return 29; // 28 -> 31, rol 29
case PPC::BGE: Inv = true; return 29; // 28 -> 31, rol 29
case PPC::BGT: Inv = false; return 30; // 29 -> 31, rol 30
case PPC::BLE: Inv = true; return 30; // 29 -> 31, rol 30
case PPC::BEQ: Inv = false; return 31; // 30 -> 31, rol 31
case PPC::BNE: Inv = true; return 31; // 30 -> 31, rol 31
}
return 0;
}
/// IndexedOpForOp - Return the indexed variant for each of the PowerPC load
/// and store immediate instructions.
static unsigned IndexedOpForOp(unsigned Opcode) {
@ -1028,8 +1044,7 @@ unsigned ISel::SelectCC(SDOperand CC, unsigned &Opc) {
// If the first operand to the select is a SETCC node, then we can fold it
// into the branch that selects which value to return.
SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
if (SetCC && CC.getOpcode() == ISD::SETCC) {
if (SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val)) {
bool U;
Opc = getBCCForSetCC(SetCC->getCondition(), U);
@ -2163,47 +2178,21 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
}
}
bool Inv = false;
unsigned CCReg = SelectCC(N, Opc);
unsigned TrueValue = MakeReg(MVT::i32);
BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
unsigned FalseValue = MakeReg(MVT::i32);
BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
// Create an iterator with which to insert the MBB for copying the false
// value and the MBB to hold the PHI instruction for this SetCC.
MachineBasicBlock *thisMBB = BB;
const BasicBlock *LLVM_BB = BB->getBasicBlock();
ilist<MachineBasicBlock>::iterator It = BB;
++It;
// thisMBB:
// ...
// cmpTY ccX, r1, r2
// %TrueValue = li 1
// bCC sinkMBB
MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
BuildMI(BB, Opc, 2).addReg(CCReg).addMBB(sinkMBB);
MachineFunction *F = BB->getParent();
F->getBasicBlockList().insert(It, copy0MBB);
F->getBasicBlockList().insert(It, sinkMBB);
// Update machine-CFG edges
BB->addSuccessor(copy0MBB);
BB->addSuccessor(sinkMBB);
// copy0MBB:
// %FalseValue = li 0
// fallthrough
BB = copy0MBB;
// Update machine-CFG edges
BB->addSuccessor(sinkMBB);
// sinkMBB:
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
BuildMI(BB, PPC::PHI, 4, Result).addReg(FalseValue)
.addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
unsigned IntCR = MakeReg(MVT::i32);
unsigned ShAmt = getCRIdxForBCC(Opc, Inv);
BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
BuildMI(BB, PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
if (Inv) {
Tmp1 = MakeReg(MVT::i32);
BuildMI(BB, PPC::RLWINM, 4, Tmp1).addReg(IntCR).addImm(ShAmt)
.addImm(31).addImm(31);
BuildMI(BB, PPC::XORI, 2, Result).addReg(Tmp1).addImm(1);
} else {
BuildMI(BB, PPC::RLWINM, 4, Result).addReg(IntCR).addImm(ShAmt)
.addImm(31).addImm(31);
}
return Result;
}
assert(0 && "Is this legal?");

4
lib/Target/PowerPC/PPCInstrFormats.td
View File

@ -392,13 +392,13 @@ class XFXForm_3<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
let Inst{31} = 0;
}
class XFXForm_5<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
class XFXForm_5<bits<6> opcode, bit mfcrf, bits<10> xo, bit ppc64, bit vmx,
dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
bits<8> FXM;
bits<5> ST;
let Inst{6-10} = ST;
let Inst{11} = 0;
let Inst{11} = mfcrf;
let Inst{12-19} = FXM;
let Inst{20} = 0;
let Inst{21-30} = xo;

4
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -370,8 +370,10 @@ def MCRF : XLForm_3<19, 0, 0, 0, (ops CRRC:$BF, CRRC:$BFA),
def MFCTR : XFXForm_1_ext<31, 339, 288, 0, 0, (ops GPRC:$rT), "mfctr $rT">;
def MFLR : XFXForm_1_ext<31, 339, 256, 0, 0, (ops GPRC:$rT), "mflr $rT">;
def MFCR : XFXForm_3<31, 19, 0, 0, (ops GPRC:$rT), "mfcr $rT">;
def MTCRF : XFXForm_5<31, 144, 0, 0, (ops CRRC:$FXM, GPRC:$rS),
def MTCRF : XFXForm_5<31, 0, 144, 0, 0, (ops CRRC:$FXM, GPRC:$rS),
"mtcrf $FXM, $rS">;
def MFCRF : XFXForm_5<31, 1, 19, 0, 0, (ops GPRC:$rT, CRRC:$FXM),
"mfcr $rT, $FXM">;
def MTCTR : XFXForm_7_ext<31, 467, 288, 0, 0, (ops GPRC:$rS), "mtctr $rS">;
def MTLR : XFXForm_7_ext<31, 467, 256, 0, 0, (ops GPRC:$rS), "mtlr $rS">;