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https://github.com/c64scene-ar/llvm-6502.git
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Pseudo-ize the t2LDMIA_RET instruction.
It's just a t2LDMIA_UPD instruction with extra codegen properties, so it doesn't need the encoding information. As a side-benefit, we now correctly recognize for instruction printing as a 'pop' instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134173 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1096,6 +1096,14 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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OutStreamer.EmitInstruction(TmpInst);
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return;
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}
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case ARM::t2LDMIA_RET: {
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// As above for LDMIA_RET. Map to the tPOP instruction.
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MCInst TmpInst;
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LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
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TmpInst.setOpcode(ARM::t2LDMIA_UPD);
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OutStreamer.EmitInstruction(TmpInst);
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return;
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}
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case ARM::tPOP_RET: {
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// As above for LDMIA_RET. Map to the tPOP instruction.
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MCInst TmpInst;
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@ -2962,28 +2962,13 @@ let Defs =
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//
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// FIXME: remove when we have a way to marking a MI with these properties.
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// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
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// operand list.
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// FIXME: Should pc be an implicit operand like PICADD, etc?
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let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
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hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
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def t2LDMIA_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
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reglist:$regs, variable_ops),
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IIC_iLoad_mBr,
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"ldmia${p}.w\t$Rn!, $regs",
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"$Rn = $wb", []> {
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bits<4> Rn;
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bits<16> regs;
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b00;
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let Inst{24-23} = 0b01; // Increment After
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let Inst{22} = 0;
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let Inst{21} = 1; // Writeback
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let Inst{20} = 1;
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let Inst{19-16} = Rn;
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let Inst{15-0} = regs;
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}
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def t2LDMIA_RET: t2PseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
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reglist:$regs, variable_ops),
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Size4Bytes, IIC_iLoad_mBr, []>,
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RegConstraint<"$Rn = $wb">;
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let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
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let isPredicable = 1 in
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@ -13,7 +13,7 @@ define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<
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; CHECK: _ZNKSs7compareERKSs:
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; CHECK: it eq
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; CHECK-NEXT: subeq{{(.w)?}} r0, r{{[0-9]+}}, r{{[0-9]+}}
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; CHECK-NEXT: ldmia.w sp!,
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; CHECK-NEXT: pop.w
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entry:
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%0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3]
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%1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i32> [#uses=3]
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