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https://github.com/c64scene-ar/llvm-6502.git
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legalize a bunch of operations that I missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19580 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -751,7 +751,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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case ISD::FP_TO_UINT:
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP:
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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case Legal:
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Tmp1 = LegalizeOp(Node->getOperand(0));
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@ -776,19 +775,30 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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case Promote:
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switch (Node->getOpcode()) {
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case ISD::ZERO_EXTEND: {
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// Mask out the high bits.
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uint64_t MaskCst =
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1ULL << (MVT::getSizeInBits(Node->getOperand(0).getValueType()))-1;
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Tmp1 = PromoteOp(Node->getOperand(0));
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Result = DAG.getNode(ISD::AND, Node->getValueType(0), Tmp1,
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DAG.getConstant(MaskCst, Node->getValueType(0)));
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case ISD::ZERO_EXTEND:
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Result = PromoteOp(Node->getOperand(0));
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Result = DAG.getNode(ISD::ZERO_EXTEND_INREG, Result.getValueType(),
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Result, Node->getOperand(0).getValueType());
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break;
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}
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case ISD::SIGN_EXTEND:
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Result = PromoteOp(Node->getOperand(0));
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Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
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Result, Node->getOperand(0).getValueType());
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break;
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case ISD::TRUNCATE:
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Result = PromoteOp(Node->getOperand(0));
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Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
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break;
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case ISD::FP_EXTEND:
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Result = PromoteOp(Node->getOperand(0));
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if (Result.getValueType() != Op.getValueType())
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// Dynamically dead while we have only 2 FP types.
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Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
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break;
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case ISD::FP_ROUND:
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Result = PromoteOp(Node->getOperand(0));
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Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Result);
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break;
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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case ISD::SINT_TO_FP:
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