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If BitWidth equals to ShtAmt, the RHSKnownZero[BitWidth-ShiftAmt-1] will

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crash the opt. Just fix this.

Test case in llvm/test/Transforms/InstCombine/2008-06-05-ashr-crash.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52003 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zhou Sheng 2008-06-05 14:23:44 +00:00
parent 411e6a5efb
commit 17183ab973
1 changed files with 1 additions and 1 deletions
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2
lib/Transforms/Scalar/InstructionCombining.cpp
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@ -1236,7 +1236,7 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, APInt DemandedMask,
// If the input sign bit is known to be zero, or if none of the top bits // If the input sign bit is known to be zero, or if none of the top bits
// are demanded, turn this into an unsigned shift right. // are demanded, turn this into an unsigned shift right.
if (RHSKnownZero[BitWidth-ShiftAmt-1] || if (BitWidth == ShiftAmt || RHSKnownZero[BitWidth-ShiftAmt-1] ||
(HighBits & ~DemandedMask) == HighBits) { (HighBits & ~DemandedMask) == HighBits) {
// Perform the logical shift right. // Perform the logical shift right.
Value *NewVal = BinaryOperator::CreateLShr( Value *NewVal = BinaryOperator::CreateLShr(