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https://github.com/c64scene-ar/llvm-6502.git
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R600/SI: Refactor the VOP3_32 tablegen class
This will allow us to use a single MachineInstr to represent instructions which behave the same but have different encodings on some subtargets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209028 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
9d99d7a185
commit
17200e3bb3
@ -355,3 +355,14 @@ int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {
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case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3);
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}
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}
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// Wrapper for Tablegen'd function. enum Subtarget is not defined in any
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// header files, so we need to wrap it in a function that takes unsigned
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// instead.
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namespace llvm {
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namespace AMDGPU {
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int getMCOpcode(uint16_t Opcode, unsigned Gen) {
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return getMCOpcode(Opcode);
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}
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}
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}
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@ -17,6 +17,7 @@
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#include "AMDGPUAsmPrinter.h"
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#include "InstPrinter/AMDGPUInstPrinter.h"
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#include "R600InstrInfo.h"
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#include "SIInstrInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/IR/Constants.h"
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@ -31,12 +32,30 @@
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using namespace llvm;
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AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx):
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Ctx(ctx)
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AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st):
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Ctx(ctx), ST(st)
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{ }
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enum AMDGPUMCInstLower::SISubtarget
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AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned Gen) const {
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switch (Gen) {
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default: return AMDGPUMCInstLower::SI;
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}
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}
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unsigned AMDGPUMCInstLower::getMCOpcode(unsigned MIOpcode) const {
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int MCOpcode = AMDGPU::getMCOpcode(MIOpcode,
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AMDGPUSubtargetToSISubtarget(ST.getGeneration()));
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if (MCOpcode == -1)
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MCOpcode = MIOpcode;
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return MCOpcode;
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}
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void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
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OutMI.setOpcode(MI->getOpcode());
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OutMI.setOpcode(getMCOpcode(MI->getOpcode()));
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for (const MachineOperand &MO : MI->explicit_operands()) {
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MCOperand MCOp;
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@ -65,7 +84,8 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
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}
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void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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AMDGPUMCInstLower MCInstLowering(OutContext);
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AMDGPUMCInstLower MCInstLowering(OutContext,
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MF->getTarget().getSubtarget<AMDGPUSubtarget>());
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#ifdef _DEBUG
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StringRef Err;
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@ -13,16 +13,30 @@
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namespace llvm {
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class AMDGPUSubtarget;
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class MCInst;
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class MCContext;
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class MachineInstr;
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class AMDGPUMCInstLower {
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// This must be kept in sync with the SISubtarget class in SIInstrInfo.td
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enum SISubtarget {
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SI = 0
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};
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MCContext &Ctx;
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const AMDGPUSubtarget &ST;
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/// Convert a member of the AMDGPUSubtarget::Generation enum to the
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/// SISubtarget enum.
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enum SISubtarget AMDGPUSubtargetToSISubtarget(unsigned Gen) const;
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/// Get the MC opcode for this MachineInstr.
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unsigned getMCOpcode(unsigned MIOpcode) const;
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public:
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AMDGPUMCInstLower(MCContext &ctx);
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AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &ST);
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/// \brief Lower a MachineInstr to an MCInst
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void lower(const MachineInstr *MI, MCInst &OutMI) const;
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@ -176,6 +176,7 @@ namespace AMDGPU {
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int getVOPe64(uint16_t Opcode);
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int getCommuteRev(uint16_t Opcode);
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int getCommuteOrig(uint16_t Opcode);
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int getMCOpcode(uint16_t Opcode, unsigned Gen);
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const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
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@ -7,6 +7,13 @@
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//
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//===----------------------------------------------------------------------===//
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// Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
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// in AMDGPUMCInstLower.h
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def SISubtarget {
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int NONE = -1;
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int SI = 0;
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}
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//===----------------------------------------------------------------------===//
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// SI DAG Nodes
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//===----------------------------------------------------------------------===//
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@ -245,6 +252,23 @@ class VOP2_REV <string revOp, bit isOrig> {
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bit IsOrig = isOrig;
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}
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class SIMCInstr <string pseudo, int subtarget> {
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string PseudoInstr = pseudo;
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int Subtarget = subtarget;
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}
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multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
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string opName> {
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def "" : InstSI <outs, ins, "", pattern>, VOP <opName>,
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SIMCInstr<OpName, SISubtarget.NONE> {
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let isPseudo = 1;
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}
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def _si : VOP3 <op, outs, ins, asm, []>, SIMCInstr<opName, SISubtarget.SI>;
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}
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// This must always be right before the operand being input modified.
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def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
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let PrintMethod = "printOperandAndMods";
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@ -364,13 +388,13 @@ multiclass VOPC_64 <bits<8> op, string opName,
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ValueType vt = untyped, PatLeaf cond = COND_NULL>
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: VOPC_Helper <op, VReg_64, VSrc_64, opName, vt, cond>;
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class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
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multiclass VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3_m <
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op, (outs VReg_32:$dst),
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(ins InputMods: $src0_modifiers, VSrc_32:$src0, InputMods:$src1_modifiers,
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VSrc_32:$src1, InputMods:$src2_modifiers, VSrc_32:$src2,
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InstFlag:$clamp, InstFlag:$omod),
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opName#" $dst, $src0_modifiers, $src1, $src2, $clamp, $omod", pattern
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>, VOP <opName>;
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opName#" $dst, $src0_modifiers, $src1, $src2, $clamp, $omod", pattern, opName
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>;
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class VOP3_64_Shift <bits <9> op, string opName, list<dag> pattern> : VOP3 <
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op, (outs VReg_64:$dst),
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@ -681,4 +705,12 @@ def isDS : InstrMapping {
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let ValueCols = [["8"]];
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}
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def getMCOpcode : InstrMapping {
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let FilterClass = "SIMCInstr";
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let RowFields = ["PseudoInstr"];
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let ColFields = ["Subtarget"];
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let KeyCol = [!cast<string>(SISubtarget.NONE)];
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let ValueCols = [[!cast<string>(SISubtarget.SI)]];
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}
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include "SIInstructions.td"
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@ -1246,41 +1246,41 @@ defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32",
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let neverHasSideEffects = 1 in {
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def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>;
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def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>;
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def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24",
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defm V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>;
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defm V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>;
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defm V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24",
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[(set i32:$dst, (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2))]
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>;
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def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24",
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defm V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24",
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[(set i32:$dst, (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2))]
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>;
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} // End neverHasSideEffects
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def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
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def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
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def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
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def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
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defm V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
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defm V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
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defm V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
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defm V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
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let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
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def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32",
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defm V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32",
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[(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))]>;
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def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32",
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defm V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32",
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[(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))]>;
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}
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def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32",
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defm V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32",
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[(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))]>;
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def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
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defm V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
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[(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))]
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>;
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def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64",
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[(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
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>;
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//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
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def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
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defm V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
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def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>;
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def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
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defm V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>;
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defm V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
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////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
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////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
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////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
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@ -1293,9 +1293,9 @@ def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
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//def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
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//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
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//def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
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def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>;
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defm V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>;
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////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
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def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>;
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defm V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>;
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def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>;
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def V_LSHL_B64 : VOP3_64_Shift <0x00000161, "V_LSHL_B64",
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@ -1321,16 +1321,16 @@ def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>;
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let isCommutable = 1 in {
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def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>;
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def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>;
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def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>;
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def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
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defm V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>;
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defm V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>;
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defm V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>;
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defm V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
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} // isCommutable = 1
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def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
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defm V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
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def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>;
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def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>;
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defm V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>;
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def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>;
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//def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
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//def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
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@ -2312,9 +2312,9 @@ defm V_RNDNE_F64 : VOP1_64 <0x00000019, "V_RNDNE_F64",
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[(set f64:$dst, (frint f64:$src0))]
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>;
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def V_QSAD_PK_U16_U8 : VOP3_32 <0x00000173, "V_QSAD_PK_U16_U8", []>;
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def V_MQSAD_U16_U8 : VOP3_32 <0x000000172, "V_MQSAD_U16_U8", []>;
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def V_MQSAD_U32_U8 : VOP3_32 <0x00000175, "V_MQSAD_U32_U8", []>;
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defm V_QSAD_PK_U16_U8 : VOP3_32 <0x00000173, "V_QSAD_PK_U16_U8", []>;
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defm V_MQSAD_U16_U8 : VOP3_32 <0x000000172, "V_MQSAD_U16_U8", []>;
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defm V_MQSAD_U32_U8 : VOP3_32 <0x00000175, "V_MQSAD_U32_U8", []>;
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def V_MAD_U64_U32 : VOP3_64 <0x00000176, "V_MAD_U64_U32", []>;
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// XXX - Does this set VCC?
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