mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
R600/SI: Refactor the VOP3_32 tablegen class
This will allow us to use a single MachineInstr to represent instructions which behave the same but have different encodings on some subtargets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209028 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
9d99d7a185
commit
17200e3bb3
@ -355,3 +355,14 @@ int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const {
|
||||
case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3);
|
||||
}
|
||||
}
|
||||
|
||||
// Wrapper for Tablegen'd function. enum Subtarget is not defined in any
|
||||
// header files, so we need to wrap it in a function that takes unsigned
|
||||
// instead.
|
||||
namespace llvm {
|
||||
namespace AMDGPU {
|
||||
int getMCOpcode(uint16_t Opcode, unsigned Gen) {
|
||||
return getMCOpcode(Opcode);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
#include "AMDGPUAsmPrinter.h"
|
||||
#include "InstPrinter/AMDGPUInstPrinter.h"
|
||||
#include "R600InstrInfo.h"
|
||||
#include "SIInstrInfo.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineInstr.h"
|
||||
#include "llvm/IR/Constants.h"
|
||||
@ -31,12 +32,30 @@
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx):
|
||||
Ctx(ctx)
|
||||
AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st):
|
||||
Ctx(ctx), ST(st)
|
||||
{ }
|
||||
|
||||
enum AMDGPUMCInstLower::SISubtarget
|
||||
AMDGPUMCInstLower::AMDGPUSubtargetToSISubtarget(unsigned Gen) const {
|
||||
switch (Gen) {
|
||||
default: return AMDGPUMCInstLower::SI;
|
||||
}
|
||||
}
|
||||
|
||||
unsigned AMDGPUMCInstLower::getMCOpcode(unsigned MIOpcode) const {
|
||||
|
||||
int MCOpcode = AMDGPU::getMCOpcode(MIOpcode,
|
||||
AMDGPUSubtargetToSISubtarget(ST.getGeneration()));
|
||||
if (MCOpcode == -1)
|
||||
MCOpcode = MIOpcode;
|
||||
|
||||
return MCOpcode;
|
||||
}
|
||||
|
||||
void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
|
||||
OutMI.setOpcode(MI->getOpcode());
|
||||
|
||||
OutMI.setOpcode(getMCOpcode(MI->getOpcode()));
|
||||
|
||||
for (const MachineOperand &MO : MI->explicit_operands()) {
|
||||
MCOperand MCOp;
|
||||
@ -65,7 +84,8 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
|
||||
}
|
||||
|
||||
void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
||||
AMDGPUMCInstLower MCInstLowering(OutContext);
|
||||
AMDGPUMCInstLower MCInstLowering(OutContext,
|
||||
MF->getTarget().getSubtarget<AMDGPUSubtarget>());
|
||||
|
||||
#ifdef _DEBUG
|
||||
StringRef Err;
|
||||
|
||||
@ -13,16 +13,30 @@
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class AMDGPUSubtarget;
|
||||
class MCInst;
|
||||
class MCContext;
|
||||
class MachineInstr;
|
||||
|
||||
class AMDGPUMCInstLower {
|
||||
|
||||
// This must be kept in sync with the SISubtarget class in SIInstrInfo.td
|
||||
enum SISubtarget {
|
||||
SI = 0
|
||||
};
|
||||
|
||||
MCContext &Ctx;
|
||||
const AMDGPUSubtarget &ST;
|
||||
|
||||
/// Convert a member of the AMDGPUSubtarget::Generation enum to the
|
||||
/// SISubtarget enum.
|
||||
enum SISubtarget AMDGPUSubtargetToSISubtarget(unsigned Gen) const;
|
||||
|
||||
/// Get the MC opcode for this MachineInstr.
|
||||
unsigned getMCOpcode(unsigned MIOpcode) const;
|
||||
|
||||
public:
|
||||
AMDGPUMCInstLower(MCContext &ctx);
|
||||
AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &ST);
|
||||
|
||||
/// \brief Lower a MachineInstr to an MCInst
|
||||
void lower(const MachineInstr *MI, MCInst &OutMI) const;
|
||||
|
||||
@ -176,6 +176,7 @@ namespace AMDGPU {
|
||||
int getVOPe64(uint16_t Opcode);
|
||||
int getCommuteRev(uint16_t Opcode);
|
||||
int getCommuteOrig(uint16_t Opcode);
|
||||
int getMCOpcode(uint16_t Opcode, unsigned Gen);
|
||||
|
||||
const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
|
||||
|
||||
|
||||
@ -7,6 +7,13 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
|
||||
// in AMDGPUMCInstLower.h
|
||||
def SISubtarget {
|
||||
int NONE = -1;
|
||||
int SI = 0;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SI DAG Nodes
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -245,6 +252,23 @@ class VOP2_REV <string revOp, bit isOrig> {
|
||||
bit IsOrig = isOrig;
|
||||
}
|
||||
|
||||
class SIMCInstr <string pseudo, int subtarget> {
|
||||
string PseudoInstr = pseudo;
|
||||
int Subtarget = subtarget;
|
||||
}
|
||||
|
||||
multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
|
||||
string opName> {
|
||||
|
||||
def "" : InstSI <outs, ins, "", pattern>, VOP <opName>,
|
||||
SIMCInstr<OpName, SISubtarget.NONE> {
|
||||
let isPseudo = 1;
|
||||
}
|
||||
|
||||
def _si : VOP3 <op, outs, ins, asm, []>, SIMCInstr<opName, SISubtarget.SI>;
|
||||
|
||||
}
|
||||
|
||||
// This must always be right before the operand being input modified.
|
||||
def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
|
||||
let PrintMethod = "printOperandAndMods";
|
||||
@ -364,13 +388,13 @@ multiclass VOPC_64 <bits<8> op, string opName,
|
||||
ValueType vt = untyped, PatLeaf cond = COND_NULL>
|
||||
: VOPC_Helper <op, VReg_64, VSrc_64, opName, vt, cond>;
|
||||
|
||||
class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
|
||||
multiclass VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3_m <
|
||||
op, (outs VReg_32:$dst),
|
||||
(ins InputMods: $src0_modifiers, VSrc_32:$src0, InputMods:$src1_modifiers,
|
||||
VSrc_32:$src1, InputMods:$src2_modifiers, VSrc_32:$src2,
|
||||
InstFlag:$clamp, InstFlag:$omod),
|
||||
opName#" $dst, $src0_modifiers, $src1, $src2, $clamp, $omod", pattern
|
||||
>, VOP <opName>;
|
||||
opName#" $dst, $src0_modifiers, $src1, $src2, $clamp, $omod", pattern, opName
|
||||
>;
|
||||
|
||||
class VOP3_64_Shift <bits <9> op, string opName, list<dag> pattern> : VOP3 <
|
||||
op, (outs VReg_64:$dst),
|
||||
@ -681,4 +705,12 @@ def isDS : InstrMapping {
|
||||
let ValueCols = [["8"]];
|
||||
}
|
||||
|
||||
def getMCOpcode : InstrMapping {
|
||||
let FilterClass = "SIMCInstr";
|
||||
let RowFields = ["PseudoInstr"];
|
||||
let ColFields = ["Subtarget"];
|
||||
let KeyCol = [!cast<string>(SISubtarget.NONE)];
|
||||
let ValueCols = [[!cast<string>(SISubtarget.SI)]];
|
||||
}
|
||||
|
||||
include "SIInstructions.td"
|
||||
|
||||
@ -1246,41 +1246,41 @@ defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32",
|
||||
|
||||
let neverHasSideEffects = 1 in {
|
||||
|
||||
def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>;
|
||||
def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>;
|
||||
def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24",
|
||||
defm V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>;
|
||||
defm V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>;
|
||||
defm V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24",
|
||||
[(set i32:$dst, (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2))]
|
||||
>;
|
||||
def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24",
|
||||
defm V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24",
|
||||
[(set i32:$dst, (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2))]
|
||||
>;
|
||||
|
||||
} // End neverHasSideEffects
|
||||
def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
|
||||
def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
|
||||
def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
|
||||
def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
|
||||
defm V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>;
|
||||
defm V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>;
|
||||
defm V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>;
|
||||
defm V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>;
|
||||
|
||||
let neverHasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
|
||||
def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32",
|
||||
defm V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32",
|
||||
[(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))]>;
|
||||
def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32",
|
||||
defm V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32",
|
||||
[(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))]>;
|
||||
}
|
||||
|
||||
def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32",
|
||||
defm V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32",
|
||||
[(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))]>;
|
||||
def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
|
||||
defm V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32",
|
||||
[(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))]
|
||||
>;
|
||||
def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64",
|
||||
[(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
|
||||
>;
|
||||
//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>;
|
||||
def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
|
||||
defm V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>;
|
||||
|
||||
def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>;
|
||||
def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
|
||||
defm V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>;
|
||||
defm V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
|
||||
////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>;
|
||||
////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>;
|
||||
////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>;
|
||||
@ -1293,9 +1293,9 @@ def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>;
|
||||
//def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>;
|
||||
//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>;
|
||||
//def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>;
|
||||
def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>;
|
||||
defm V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>;
|
||||
////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>;
|
||||
def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>;
|
||||
defm V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>;
|
||||
def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>;
|
||||
|
||||
def V_LSHL_B64 : VOP3_64_Shift <0x00000161, "V_LSHL_B64",
|
||||
@ -1321,16 +1321,16 @@ def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>;
|
||||
|
||||
let isCommutable = 1 in {
|
||||
|
||||
def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>;
|
||||
def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>;
|
||||
def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>;
|
||||
def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
|
||||
defm V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>;
|
||||
defm V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>;
|
||||
defm V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>;
|
||||
defm V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>;
|
||||
|
||||
} // isCommutable = 1
|
||||
|
||||
def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
|
||||
defm V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>;
|
||||
def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>;
|
||||
def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>;
|
||||
defm V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>;
|
||||
def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>;
|
||||
//def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>;
|
||||
//def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>;
|
||||
@ -2312,9 +2312,9 @@ defm V_RNDNE_F64 : VOP1_64 <0x00000019, "V_RNDNE_F64",
|
||||
[(set f64:$dst, (frint f64:$src0))]
|
||||
>;
|
||||
|
||||
def V_QSAD_PK_U16_U8 : VOP3_32 <0x00000173, "V_QSAD_PK_U16_U8", []>;
|
||||
def V_MQSAD_U16_U8 : VOP3_32 <0x000000172, "V_MQSAD_U16_U8", []>;
|
||||
def V_MQSAD_U32_U8 : VOP3_32 <0x00000175, "V_MQSAD_U32_U8", []>;
|
||||
defm V_QSAD_PK_U16_U8 : VOP3_32 <0x00000173, "V_QSAD_PK_U16_U8", []>;
|
||||
defm V_MQSAD_U16_U8 : VOP3_32 <0x000000172, "V_MQSAD_U16_U8", []>;
|
||||
defm V_MQSAD_U32_U8 : VOP3_32 <0x00000175, "V_MQSAD_U32_U8", []>;
|
||||
def V_MAD_U64_U32 : VOP3_64 <0x00000176, "V_MAD_U64_U32", []>;
|
||||
|
||||
// XXX - Does this set VCC?
|
||||
|
||||
Loading…
Reference in New Issue
Block a user