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X86: Emit vector sext as shuffle + sra if vpmovsx is not available.
Also loosen the SSSE3 dependency a bit, expanded pshufb + psra is still better than scalarized loads. Fixes PR14590. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170984 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer
parent
b44c1f90e4
commit
17347912b4
@ -16043,14 +16043,14 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
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ISD::LoadExtType Ext = Ld->getExtensionType();
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// If this is a vector EXT Load then attempt to optimize it using a
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// shuffle. We need SSSE3 shuffles.
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// SEXT loads are suppoted starting SSE41.
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// We generate X86ISD::VSEXT for them.
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// shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
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// expansion is still better than scalar code.
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// We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
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// emit a shuffle and a arithmetic shift.
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// TODO: It is possible to support ZExt by zeroing the undef values
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// during the shuffle phase or after the shuffle.
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if (RegVT.isVector() && RegVT.isInteger() &&
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((Ext == ISD::EXTLOAD && Subtarget->hasSSSE3()) ||
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(Ext == ISD::SEXTLOAD && Subtarget->hasSSE41()))){
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if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
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(Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
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assert(MemVT != RegVT && "Cannot extend to the same type");
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assert(MemVT.isVector() && "Must load a vector from memory");
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@ -16143,9 +16143,40 @@ static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
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unsigned SizeRatio = RegSz/MemSz;
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if (Ext == ISD::SEXTLOAD) {
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SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
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return DCI.CombineTo(N, Sext, TF, true);
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// If we have SSE4.1 we can directly emit a VSEXT node.
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if (Subtarget->hasSSE41()) {
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SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
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return DCI.CombineTo(N, Sext, TF, true);
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}
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// Otherwise we'll shuffle the small elements in the high bits of the
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// larger type and perform an arithmetic shift. If the shift is not legal
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// it's better to scalarize.
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if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
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return SDValue();
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// Redistribute the loaded elements into the different locations.
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SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
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for (unsigned i = 0; i != NumElems; ++i)
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ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
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SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
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DAG.getUNDEF(WideVecVT),
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&ShuffleVec[0]);
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Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
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// Build the arithmetic shift.
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unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
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MemVT.getVectorElementType().getSizeInBits();
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SmallVector<SDValue, 8> C(NumElems,
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DAG.getConstant(Amt, RegVT.getScalarType()));
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SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, RegVT, &C[0], C.size());
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Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff, BV);
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return DCI.CombineTo(N, Shuff, TF, true);
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}
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// Redistribute the loaded elements into the different locations.
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SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
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for (unsigned i = 0; i != NumElems; ++i)
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@ -1,69 +1,142 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s -check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSSE3
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=pentium4 | FileCheck %s -check-prefix=SSE2
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define <8 x i32> @sext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
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;CHECK: sext_8i16_to_8i32
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;CHECK: vpmovsxwd
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; AVX: sext_8i16_to_8i32
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; AVX: vpmovsxwd
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%B = sext <8 x i16> %A to <8 x i32>
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ret <8 x i32>%B
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}
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define <4 x i64> @sext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
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;CHECK: sext_4i32_to_4i64
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;CHECK: vpmovsxdq
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; AVX: sext_4i32_to_4i64
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; AVX: vpmovsxdq
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%B = sext <4 x i32> %A to <4 x i64>
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ret <4 x i64>%B
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}
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; CHECK: load_sext_test1
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; CHECK: vpmovsxwd (%r{{[^,]*}}), %xmm{{.*}}
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; CHECK: ret
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; AVX: load_sext_test1
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; AVX: vpmovsxwd (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test1
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; SSSE3: movq
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; SSSE3: punpcklwd %xmm{{.*}}, %xmm{{.*}}
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; SSSE3: psrad $16
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; SSSE3: ret
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; SSE2: load_sext_test1
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; SSE2: movq
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; SSE2: punpcklwd %xmm{{.*}}, %xmm{{.*}}
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; SSE2: psrad $16
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; SSE2: ret
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define <4 x i32> @load_sext_test1(<4 x i16> *%ptr) {
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%X = load <4 x i16>* %ptr
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%Y = sext <4 x i16> %X to <4 x i32>
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ret <4 x i32>%Y
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}
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; CHECK: load_sext_test2
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; CHECK: vpmovsxbd (%r{{[^,]*}}), %xmm{{.*}}
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; CHECK: ret
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; AVX: load_sext_test2
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; AVX: vpmovsxbd (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test2
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; SSSE3: movd
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; SSSE3: pshufb
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; SSSE3: psrad $24
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; SSSE3: ret
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; SSE2: load_sext_test2
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; SSE2: movl
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; SSE2: psrad $24
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; SSE2: ret
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define <4 x i32> @load_sext_test2(<4 x i8> *%ptr) {
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%X = load <4 x i8>* %ptr
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%Y = sext <4 x i8> %X to <4 x i32>
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ret <4 x i32>%Y
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}
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; CHECK: load_sext_test3
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; CHECK: vpmovsxbq (%r{{[^,]*}}), %xmm{{.*}}
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; CHECK: ret
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; AVX: load_sext_test3
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; AVX: vpmovsxbq (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test3
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; SSSE3: movsbq
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; SSSE3: movsbq
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; SSSE3: punpcklqdq
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; SSSE3: ret
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; SSE2: load_sext_test3
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; SSE2: movsbq
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; SSE2: movsbq
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; SSE2: punpcklqdq
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; SSE2: ret
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define <2 x i64> @load_sext_test3(<2 x i8> *%ptr) {
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%X = load <2 x i8>* %ptr
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%Y = sext <2 x i8> %X to <2 x i64>
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ret <2 x i64>%Y
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}
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; CHECK: load_sext_test4
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; CHECK: vpmovsxwq (%r{{[^,]*}}), %xmm{{.*}}
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; CHECK: ret
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; AVX: load_sext_test4
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; AVX: vpmovsxwq (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test4
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; SSSE3: movswq
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; SSSE3: movswq
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; SSSE3: punpcklqdq
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; SSSE3: ret
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; SSE2: load_sext_test4
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; SSE2: movswq
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; SSE2: movswq
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; SSE2: punpcklqdq
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; SSE2: ret
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define <2 x i64> @load_sext_test4(<2 x i16> *%ptr) {
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%X = load <2 x i16>* %ptr
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%Y = sext <2 x i16> %X to <2 x i64>
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ret <2 x i64>%Y
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}
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; CHECK: load_sext_test5
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; CHECK: vpmovsxdq (%r{{[^,]*}}), %xmm{{.*}}
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; CHECK: ret
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; AVX: load_sext_test5
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; AVX: vpmovsxdq (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test5
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; SSSE3: movslq
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; SSSE3: movslq
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; SSSE3: punpcklqdq
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; SSSE3: ret
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; SSE2: load_sext_test5
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; SSE2: movslq
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; SSE2: movslq
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; SSE2: punpcklqdq
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; SSE2: ret
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define <2 x i64> @load_sext_test5(<2 x i32> *%ptr) {
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%X = load <2 x i32>* %ptr
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%Y = sext <2 x i32> %X to <2 x i64>
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ret <2 x i64>%Y
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}
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; CHECK: load_sext_test6
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; CHECK: vpmovsxbw (%r{{[^,]*}}), %xmm{{.*}}
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; CHECK: ret
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; AVX: load_sext_test6
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; AVX: vpmovsxbw (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test6
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; SSSE3: movq
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; SSSE3: punpcklbw
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; SSSE3: psraw $8
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; SSSE3: ret
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; SSE2: load_sext_test6
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; SSE2: movq
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; SSE2: punpcklbw
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; SSE2: psraw $8
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; SSE2: ret
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define <8 x i16> @load_sext_test6(<8 x i8> *%ptr) {
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%X = load <8 x i8>* %ptr
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%Y = sext <8 x i8> %X to <8 x i16>
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