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Use llvm_unreachable instead of assert(0)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196971 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2013-12-10 21:37:42 +00:00
parent b59d46efa5
commit 17427fa9bb
9 changed files with 18 additions and 20 deletions
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2
lib/Target/R600/AMDGPUAsmPrinter.cpp
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@ -257,7 +257,7 @@ void AMDGPUAsmPrinter::findNumUsedRegistersSI(MachineFunction &MF,
isSGPR = false;
width = 16;
} else {
assert(!"Unknown register class");
llvm_unreachable("Unknown register class");
}
hwReg = RI->getEncodingValue(reg) & 0xff;
maxUsed = hwReg + width - 1;

8
lib/Target/R600/AMDGPUISelLowering.cpp
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@ -254,8 +254,8 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
switch (Op.getOpcode()) {
default:
Op.getNode()->dump();
assert(0 && "Custom lowering code for this"
"instruction is not implemented yet!");
llvm_unreachable("Custom lowering code for this"
"instruction is not implemented yet!");
break;
// AMDIL DAG lowering
case ISD::SDIV: return LowerSDIV(Op, DAG);
@ -455,7 +455,7 @@ SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
case ISD::SETTRUE2:
case ISD::SETUO:
case ISD::SETO:
assert(0 && "Operation should already be optimised !");
llvm_unreachable("Operation should already be optimised!");
case ISD::SETULE:
case ISD::SETULT:
case ISD::SETOLE:
@ -479,7 +479,7 @@ SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
}
case ISD::SETCC_INVALID:
assert(0 && "Invalid setcc condcode !");
llvm_unreachable("Invalid setcc condcode!");
}
return Op;
}

4
lib/Target/R600/AMDGPUInstrInfo.cpp
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@ -110,7 +110,7 @@ AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
assert(!"Not Implemented");
llvm_unreachable("Not Implemented");
}
void
@ -119,7 +119,7 @@ AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
assert(!"Not Implemented");
llvm_unreachable("Not Implemented");
}
bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {

2
lib/Target/R600/AMDGPURegisterInfo.cpp
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@ -38,7 +38,7 @@ void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS) const {
assert(!"Subroutines not supported yet");
llvm_unreachable("Subroutines not supported yet");
}
unsigned AMDGPURegisterInfo::getFrameRegister(const MachineFunction &MF) const {

4
lib/Target/R600/R600ISelLowering.cpp
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@ -977,7 +977,7 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
HWFalse = DAG.getConstant(0, CompareVT);
}
else {
assert(!"Unhandled value type in LowerSELECT_CC");
llvm_unreachable("Unhandled value type in LowerSELECT_CC");
}
// Lower this unsupported SELECT_CC into a combination of two supported
@ -1099,7 +1099,7 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
Ptr, DAG.getConstant(2, MVT::i32)));
if (StoreNode->isTruncatingStore() || StoreNode->isIndexed()) {
assert(!"Truncated and indexed stores not supported yet");
llvm_unreachable("Truncated and indexed stores not supported yet");
} else {
Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
}

2
lib/Target/R600/R600OptimizeVectorRegisters.cpp
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@ -63,7 +63,7 @@ public:
DenseMap<unsigned, unsigned> RegToChan;
std::vector<unsigned> UndefReg;
RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
assert (MI->getOpcode() == AMDGPU::REG_SEQUENCE);
assert(MI->getOpcode() == AMDGPU::REG_SEQUENCE);
for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) {
MachineOperand &MO = Instr->getOperand(i);
unsigned Chan = Instr->getOperand(i + 1).getImm();

2
lib/Target/R600/SIAnnotateControlFlow.cpp
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@ -253,7 +253,7 @@ void SIAnnotateControlFlow::handleLoopCondition(Value *Cond) {
PhiInserter.AddAvailableValue(Parent, Ret);
} else {
assert(0 && "Unhandled loop condition!");
llvm_unreachable("Unhandled loop condition!");
}
}

5
lib/Target/R600/SIInstrInfo.h
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@ -60,7 +60,10 @@ public:
virtual MachineInstr *commuteInstruction(MachineInstr *MI,
bool NewMI=false) const;
virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
virtual unsigned getIEQOpcode() const {
llvm_unreachable("Unimplemented");
}
MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
MachineBasicBlock::iterator I,
unsigned DstReg, unsigned SrcReg) const;

9
lib/Target/R600/SILowerControlFlow.cpp
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@ -283,16 +283,11 @@ void SILowerControlFlowPass::EndCf(MachineInstr &MI) {
}
void SILowerControlFlowPass::Branch(MachineInstr &MI) {
MachineBasicBlock *Next = MI.getParent()->getNextNode();
MachineBasicBlock *Target = MI.getOperand(0).getMBB();
if (Target == Next)
MI.eraseFromParent();
else
assert(0);
assert(MI.getOperand(0).getMBB() == MI.getParent()->getNextNode());
MI.eraseFromParent();
}
void SILowerControlFlowPass::Kill(MachineInstr &MI) {
MachineBasicBlock &MBB = *MI.getParent();
DebugLoc DL = MI.getDebugLoc();