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Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from
floating point add/sub of appropriate shuffle vectors. Does not synthesize the 256 bit AVX versions because they work differently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140332 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands
parent
d102a03b36
commit
17470bee5f
@ -1137,6 +1137,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setTargetDAGCombine(ISD::OR);
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setTargetDAGCombine(ISD::AND);
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setTargetDAGCombine(ISD::ADD);
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setTargetDAGCombine(ISD::FADD);
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setTargetDAGCombine(ISD::FSUB);
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setTargetDAGCombine(ISD::SUB);
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setTargetDAGCombine(ISD::LOAD);
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setTargetDAGCombine(ISD::STORE);
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@ -10647,6 +10649,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::FMIN: return "X86ISD::FMIN";
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case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
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case X86ISD::FRCP: return "X86ISD::FRCP";
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case X86ISD::FHADD: return "X86ISD::FHADD";
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case X86ISD::FHSUB: return "X86ISD::FHSUB";
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case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
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case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
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case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
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@ -13738,6 +13742,150 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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/// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
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/// and return the operands for the horizontal operation in LHS and RHS. A
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/// horizontal operation performs the binary operation on successive elements
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/// of its first operand, then on successive elements of its second operand,
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/// returning the resulting values in a vector. For example, if
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/// A = < float a0, float a1, float a2, float a3 >
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/// and
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/// B = < float b0, float b1, float b2, float b3 >
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/// then the result of doing a horizontal operation on A and B is
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/// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
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/// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
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/// A horizontal-op B, for some already available A and B, and if so then LHS is
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/// set to A, RHS to B, and the routine returns 'true'.
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/// Note that the binary operation should have the property that if one of the
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/// operands is UNDEF then the result is UNDEF.
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static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool isCommutative) {
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// Look for the following pattern: if
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// A = < float a0, float a1, float a2, float a3 >
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// B = < float b0, float b1, float b2, float b3 >
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// and
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// LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
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// RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
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// then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
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// which is A horizontal-op B.
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// At least one of the operands should be a vector shuffle.
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if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
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RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
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return false;
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EVT VT = LHS.getValueType();
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unsigned N = VT.getVectorNumElements();
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// View LHS in the form
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// LHS = VECTOR_SHUFFLE A, B, LMask
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// If LHS is not a shuffle then pretend it is the shuffle
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// LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
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// NOTE: in what follows a default initialized SDValue represents an UNDEF of
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// type VT.
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SDValue A, B;
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SmallVector<int, 8> LMask(N);
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if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
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if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
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A = LHS.getOperand(0);
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if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
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B = LHS.getOperand(1);
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cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(LMask);
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} else {
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if (LHS.getOpcode() != ISD::UNDEF)
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A = LHS;
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for (unsigned i = 0; i != N; ++i)
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LMask[i] = i;
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}
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// Likewise, view RHS in the form
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// RHS = VECTOR_SHUFFLE C, D, RMask
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SDValue C, D;
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SmallVector<int, 8> RMask(N);
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if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
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if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
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C = RHS.getOperand(0);
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if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
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D = RHS.getOperand(1);
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cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(RMask);
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} else {
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if (RHS.getOpcode() != ISD::UNDEF)
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C = RHS;
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for (unsigned i = 0; i != N; ++i)
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RMask[i] = i;
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}
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// Check that the shuffles are both shuffling the same vectors.
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if (!(A == C && B == D) && !(A == D && B == C))
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return false;
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// If everything is UNDEF then bail out: it would be better to fold to UNDEF.
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if (!A.getNode() && !B.getNode())
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return false;
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// If A and B occur in reverse order in RHS, then "swap" them (which means
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// rewriting the mask).
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if (A != C)
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for (unsigned i = 0; i != N; ++i) {
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unsigned Idx = RMask[i];
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if (Idx < N)
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RMask[i] += N;
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else if (Idx < 2*N)
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RMask[i] -= N;
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}
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// At this point LHS and RHS are equivalent to
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// LHS = VECTOR_SHUFFLE A, B, LMask
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// RHS = VECTOR_SHUFFLE A, B, RMask
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// Check that the masks correspond to performing a horizontal operation.
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for (unsigned i = 0; i != N; ++i) {
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unsigned LIdx = LMask[i], RIdx = RMask[i];
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// Ignore any UNDEF components.
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if (LIdx >= 2*N || RIdx >= 2*N || (!A.getNode() && (LIdx < N || RIdx < N))
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|| (!B.getNode() && (LIdx >= N || RIdx >= N)))
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continue;
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// Check that successive elements are being operated on. If not, this is
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// not a horizontal operation.
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if (!(LIdx == 2*i && RIdx == 2*i + 1) &&
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!(isCommutative && LIdx == 2*i + 1 && RIdx == 2*i))
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return false;
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}
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LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
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RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
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return true;
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}
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/// PerformFADDCombine - Do target-specific dag combines on floating point adds.
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static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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EVT VT = N->getValueType(0);
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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// Try to synthesize horizontal adds from adds of shuffles.
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if ((Subtarget->hasSSE3() || Subtarget->hasAVX()) &&
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(VT == MVT::v4f32 || VT == MVT::v2f64) &&
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isHorizontalBinOp(LHS, RHS, true))
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return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
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return SDValue();
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}
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/// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
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static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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EVT VT = N->getValueType(0);
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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// Try to synthesize horizontal subs from subs of shuffles.
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if ((Subtarget->hasSSE3() || Subtarget->hasAVX()) &&
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(VT == MVT::v4f32 || VT == MVT::v2f64) &&
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isHorizontalBinOp(LHS, RHS, false))
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return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
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return SDValue();
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}
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/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
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/// X86ISD::FXOR nodes.
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static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
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@ -13975,6 +14123,8 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
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case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
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case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
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case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
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case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
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case X86ISD::FXOR:
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case X86ISD::FOR: return PerformFORCombine(N, DAG);
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case X86ISD::FAND: return PerformFANDCombine(N, DAG);
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@ -178,6 +178,12 @@ namespace llvm {
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/// BLEND family of opcodes
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BLENDV,
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/// FHADD - Floating point horizontal add.
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FHADD,
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/// FHSUB - Floating point horizontal sub.
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FHSUB,
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/// FMAX, FMIN - Floating point max and min.
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///
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FMAX, FMIN,
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@ -39,6 +39,8 @@ def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
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def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
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def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
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def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
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def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
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def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
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def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
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def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
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def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>;
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@ -4714,62 +4714,122 @@ let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
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// Horizontal ops
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multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
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X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
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X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
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def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
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[(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
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def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
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[(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
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}
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multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
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X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
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X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
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def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
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[(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
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def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
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[(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
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}
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let Predicates = [HasAVX] in {
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defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
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int_x86_sse3_hadd_ps, 0>, VEX_4V;
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X86fhadd, 0>, VEX_4V;
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defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
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int_x86_sse3_hadd_pd, 0>, VEX_4V;
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X86fhadd, 0>, VEX_4V;
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defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
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int_x86_sse3_hsub_ps, 0>, VEX_4V;
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X86fhsub, 0>, VEX_4V;
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defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
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int_x86_sse3_hsub_pd, 0>, VEX_4V;
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X86fhsub, 0>, VEX_4V;
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defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
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int_x86_avx_hadd_ps_256, 0>, VEX_4V;
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X86fhadd, 0>, VEX_4V;
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defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
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int_x86_avx_hadd_pd_256, 0>, VEX_4V;
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X86fhadd, 0>, VEX_4V;
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defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
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int_x86_avx_hsub_ps_256, 0>, VEX_4V;
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X86fhsub, 0>, VEX_4V;
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defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
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int_x86_avx_hsub_pd_256, 0>, VEX_4V;
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X86fhsub, 0>, VEX_4V;
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}
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let Predicates = [HasAVX] in {
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def : Pat<(int_x86_sse3_hadd_ps (v4f32 VR128:$src1), VR128:$src2),
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(VHADDPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(int_x86_sse3_hadd_ps (v4f32 VR128:$src1), (memop addr:$src2)),
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(VHADDPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(int_x86_sse3_hadd_pd (v2f64 VR128:$src1), VR128:$src2),
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(VHADDPDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(int_x86_sse3_hadd_pd (v2f64 VR128:$src1), (memop addr:$src2)),
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(VHADDPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(int_x86_sse3_hsub_ps (v4f32 VR128:$src1), VR128:$src2),
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(VHSUBPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(int_x86_sse3_hsub_ps (v4f32 VR128:$src1), (memop addr:$src2)),
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(VHSUBPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(int_x86_sse3_hsub_pd (v2f64 VR128:$src1), VR128:$src2),
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(VHSUBPDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(int_x86_sse3_hsub_pd (v2f64 VR128:$src1), (memop addr:$src2)),
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(VHSUBPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(int_x86_avx_hadd_ps_256 (v8f32 VR256:$src1), VR256:$src2),
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(VHADDPSYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(int_x86_avx_hadd_ps_256 (v8f32 VR256:$src1), (memop addr:$src2)),
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(VHADDPSYrm VR256:$src1, addr:$src2)>;
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def : Pat<(int_x86_avx_hadd_pd_256 (v4f64 VR256:$src1), VR256:$src2),
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(VHADDPDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(int_x86_avx_hadd_pd_256 (v4f64 VR256:$src1), (memop addr:$src2)),
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(VHADDPDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(int_x86_avx_hsub_ps_256 (v8f32 VR256:$src1), VR256:$src2),
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(VHSUBPSYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(int_x86_avx_hsub_ps_256 (v8f32 VR256:$src1), (memop addr:$src2)),
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(VHSUBPSYrm VR256:$src1, addr:$src2)>;
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def : Pat<(int_x86_avx_hsub_pd_256 (v4f64 VR256:$src1), VR256:$src2),
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(VHSUBPDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(int_x86_avx_hsub_pd_256 (v4f64 VR256:$src1), (memop addr:$src2)),
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(VHSUBPDYrm VR256:$src1, addr:$src2)>;
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}
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let Constraints = "$src1 = $dst" in {
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defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
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int_x86_sse3_hadd_ps>;
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defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
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int_x86_sse3_hadd_pd>;
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defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
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int_x86_sse3_hsub_ps>;
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defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
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int_x86_sse3_hsub_pd>;
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||||
defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
|
||||
defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
|
||||
defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
|
||||
defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
|
||||
}
|
||||
|
||||
let Predicates = [HasSSE3] in {
|
||||
def : Pat<(int_x86_sse3_hadd_ps (v4f32 VR128:$src1), VR128:$src2),
|
||||
(HADDPSrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(int_x86_sse3_hadd_ps (v4f32 VR128:$src1), (memop addr:$src2)),
|
||||
(HADDPSrm VR128:$src1, addr:$src2)>;
|
||||
|
||||
def : Pat<(int_x86_sse3_hadd_pd (v2f64 VR128:$src1), VR128:$src2),
|
||||
(HADDPDrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(int_x86_sse3_hadd_pd (v2f64 VR128:$src1), (memop addr:$src2)),
|
||||
(HADDPDrm VR128:$src1, addr:$src2)>;
|
||||
|
||||
def : Pat<(int_x86_sse3_hsub_ps (v4f32 VR128:$src1), VR128:$src2),
|
||||
(HSUBPSrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(int_x86_sse3_hsub_ps (v4f32 VR128:$src1), (memop addr:$src2)),
|
||||
(HSUBPSrm VR128:$src1, addr:$src2)>;
|
||||
|
||||
def : Pat<(int_x86_sse3_hsub_pd (v2f64 VR128:$src1), VR128:$src2),
|
||||
(HSUBPDrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(int_x86_sse3_hsub_pd (v2f64 VR128:$src1), (memop addr:$src2)),
|
||||
(HSUBPDrm VR128:$src1, addr:$src2)>;
|
||||
}
|
||||
|
||||
//===---------------------------------------------------------------------===//
|
||||
|
||||
194
test/CodeGen/X86/haddsub.ll
Normal file
194
test/CodeGen/X86/haddsub.ll
Normal file
@ -0,0 +1,194 @@
|
||||
; RUN: llc < %s -march=x86-64 -mattr=+sse3,-avx | FileCheck %s -check-prefix=SSE3
|
||||
; RUN: llc < %s -march=x86-64 -mattr=-sse3,+avx | FileCheck %s -check-prefix=AVX
|
||||
|
||||
; SSE3: haddpd1:
|
||||
; SSE3-NOT: vhaddpd
|
||||
; SSE3: haddpd
|
||||
; AVX: haddpd1:
|
||||
; AVX: vhaddpd
|
||||
define <2 x double> @haddpd1(<2 x double> %x, <2 x double> %y) {
|
||||
%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
|
||||
%b = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 3>
|
||||
%r = fadd <2 x double> %a, %b
|
||||
ret <2 x double> %r
|
||||
}
|
||||
|
||||
; SSE3: haddpd2:
|
||||
; SSE3-NOT: vhaddpd
|
||||
; SSE3: haddpd
|
||||
; AVX: haddpd2:
|
||||
; AVX: vhaddpd
|
||||
define <2 x double> @haddpd2(<2 x double> %x, <2 x double> %y) {
|
||||
%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 2>
|
||||
%b = shufflevector <2 x double> %y, <2 x double> %x, <2 x i32> <i32 2, i32 1>
|
||||
%r = fadd <2 x double> %a, %b
|
||||
ret <2 x double> %r
|
||||
}
|
||||
|
||||
; SSE3: haddpd3:
|
||||
; SSE3-NOT: vhaddpd
|
||||
; SSE3: haddpd
|
||||
; AVX: haddpd3:
|
||||
; AVX: vhaddpd
|
||||
define <2 x double> @haddpd3(<2 x double> %x) {
|
||||
%a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
|
||||
%b = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 1, i32 undef>
|
||||
%r = fadd <2 x double> %a, %b
|
||||
ret <2 x double> %r
|
||||
}
|
||||
|
||||
; SSE3: haddps1:
|
||||
; SSE3-NOT: vhaddps
|
||||
; SSE3: haddps
|
||||
; AVX: haddps1:
|
||||
; AVX: vhaddps
|
||||
define <4 x float> @haddps1(<4 x float> %x, <4 x float> %y) {
|
||||
%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%b = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
|
||||
%r = fadd <4 x float> %a, %b
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
; SSE3: haddps2:
|
||||
; SSE3-NOT: vhaddps
|
||||
; SSE3: haddps
|
||||
; AVX: haddps2:
|
||||
; AVX: vhaddps
|
||||
define <4 x float> @haddps2(<4 x float> %x, <4 x float> %y) {
|
||||
%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 2, i32 5, i32 6>
|
||||
%b = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 4, i32 7, i32 0, i32 3>
|
||||
%r = fadd <4 x float> %a, %b
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
; SSE3: haddps3:
|
||||
; SSE3-NOT: vhaddps
|
||||
; SSE3: haddps
|
||||
; AVX: haddps3:
|
||||
; AVX: vhaddps
|
||||
define <4 x float> @haddps3(<4 x float> %x) {
|
||||
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
|
||||
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
|
||||
%r = fadd <4 x float> %a, %b
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
; SSE3: haddps4:
|
||||
; SSE3-NOT: vhaddps
|
||||
; SSE3: haddps
|
||||
; AVX: haddps4:
|
||||
; AVX: vhaddps
|
||||
define <4 x float> @haddps4(<4 x float> %x) {
|
||||
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
|
||||
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
|
||||
%r = fadd <4 x float> %a, %b
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
; SSE3: haddps5:
|
||||
; SSE3-NOT: vhaddps
|
||||
; SSE3: haddps
|
||||
; AVX: haddps5:
|
||||
; AVX: vhaddps
|
||||
define <4 x float> @haddps5(<4 x float> %x) {
|
||||
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 3, i32 undef, i32 undef>
|
||||
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 undef, i32 undef>
|
||||
%r = fadd <4 x float> %a, %b
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
; SSE3: haddps6:
|
||||
; SSE3-NOT: vhaddps
|
||||
; SSE3: haddps
|
||||
; AVX: haddps6:
|
||||
; AVX: vhaddps
|
||||
define <4 x float> @haddps6(<4 x float> %x) {
|
||||
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
|
||||
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
|
||||
%r = fadd <4 x float> %a, %b
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
; SSE3: haddps7:
|
||||
; SSE3-NOT: vhaddps
|
||||
; SSE3: haddps
|
||||
; AVX: haddps7:
|
||||
; AVX: vhaddps
|
||||
define <4 x float> @haddps7(<4 x float> %x) {
|
||||
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 undef>
|
||||
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef>
|
||||
%r = fadd <4 x float> %a, %b
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
; SSE3: hsubpd1:
|
||||
; SSE3-NOT: vhsubpd
|
||||
; SSE3: hsubpd
|
||||
; AVX: hsubpd1:
|
||||
; AVX: vhsubpd
|
||||
define <2 x double> @hsubpd1(<2 x double> %x, <2 x double> %y) {
|
||||
%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
|
||||
%b = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 3>
|
||||
%r = fsub <2 x double> %a, %b
|
||||
ret <2 x double> %r
|
||||
}
|
||||
|
||||
; SSE3: hsubpd2:
|
||||
; SSE3-NOT: vhsubpd
|
||||
; SSE3: hsubpd
|
||||
; AVX: hsubpd2:
|
||||
; AVX: vhsubpd
|
||||
define <2 x double> @hsubpd2(<2 x double> %x) {
|
||||
%a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
|
||||
%b = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 1, i32 undef>
|
||||
%r = fsub <2 x double> %a, %b
|
||||
ret <2 x double> %r
|
||||
}
|
||||
|
||||
; SSE3: hsubps1:
|
||||
; SSE3-NOT: vhsubps
|
||||
; SSE3: hsubps
|
||||
; AVX: hsubps1:
|
||||
; AVX: vhsubps
|
||||
define <4 x float> @hsubps1(<4 x float> %x, <4 x float> %y) {
|
||||
%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
||||
%b = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
|
||||
%r = fsub <4 x float> %a, %b
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
; SSE3: hsubps2:
|
||||
; SSE3-NOT: vhsubps
|
||||
; SSE3: hsubps
|
||||
; AVX: hsubps2:
|
||||
; AVX: vhsubps
|
||||
define <4 x float> @hsubps2(<4 x float> %x) {
|
||||
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
|
||||
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
|
||||
%r = fsub <4 x float> %a, %b
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
; SSE3: hsubps3:
|
||||
; SSE3-NOT: vhsubps
|
||||
; SSE3: hsubps
|
||||
; AVX: hsubps3:
|
||||
; AVX: vhsubps
|
||||
define <4 x float> @hsubps3(<4 x float> %x) {
|
||||
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
|
||||
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
|
||||
%r = fsub <4 x float> %a, %b
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
; SSE3: hsubps4:
|
||||
; SSE3-NOT: vhsubps
|
||||
; SSE3: hsubps
|
||||
; AVX: hsubps4:
|
||||
; AVX: vhsubps
|
||||
define <4 x float> @hsubps4(<4 x float> %x) {
|
||||
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
|
||||
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
|
||||
%r = fsub <4 x float> %a, %b
|
||||
ret <4 x float> %r
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user