diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 1d29ff88914..3fb8ebea402 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -142,9 +142,20 @@ def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
 // FP Binary Operations.
 //
 
-def VADDD  : ADbI<0b11100, 0b11, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
-                 IIC_fpALU64, "vadd", ".f64\t$dst, $a, $b",
-                 [(set DPR:$dst, (fadd DPR:$a, (f64 DPR:$b)))]>;
+def VADDD  : ADbI<0b11100, 0b11, 0, 0, (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
+                 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
+                 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]> {
+  bits<5> Dd;
+  bits<5> Dn;
+  bits<5> Dm;
+
+  let Inst{3-0}   = Dm{3-0};
+  let Inst{5}     = Dm{4};
+  let Inst{19-16} = Dn{3-0};
+  let Inst{7}     = Dn{4};
+  let Inst{15-12} = Dd{3-0};
+  let Inst{22}    = Dd{4};
+}
 
 def VADDS  : ASbIn<0b11100, 0b11, 0, 0, (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
                   IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
diff --git a/test/MC/ARM/simple-fp-encoding.ll b/test/MC/ARM/simple-fp-encoding.ll
new file mode 100644
index 00000000000..755ec072d1f
--- /dev/null
+++ b/test/MC/ARM/simple-fp-encoding.ll
@@ -0,0 +1,23 @@
+;RUN: llc -mtriple=armv7-apple-darwin -mcpu=cortex-a8 -mattr=-neonfp -show-mc-encoding < %s | FileCheck %s
+
+
+; FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
+;        should run on .s source files rather than using llc to generate the
+;        assembly.
+
+
+define arm_aapcscc float @f1(float %a, float %b) nounwind {
+entry:
+; CHECK: f1
+; CHECK: vadd.f32 s0, s1, s0  @ encoding: [0x80,0x0a,0x30,0xee]
+  %add = fadd float %a, %b
+  ret float %add
+}
+
+define arm_aapcscc double @f2(double %a, double %b) nounwind {
+entry:
+; CHECK: f2
+; CHECK: vadd.f64 d16, d17, d16  @ encoding: [0xa0,0x0b,0x71,0xee]
+  %add = fadd double %a, %b
+  ret double %add
+}