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https://github.com/c64scene-ar/llvm-6502.git
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AVX-512: Added masked SHIFT commands, more encoding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189005 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
7ddda4704c
commit
1765e74c15
lib/Target/X86
utils/TableGen
@ -868,11 +868,12 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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case X86II::MRM6r: case X86II::MRM7r:
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// MRM0r-MRM7r instructions forms:
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// dst(VEX_4V), src(ModR/M), imm8
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VEX_4V = getVEXRegisterEncoding(MI, CurOp);
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if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
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EVEX_V2 = 0x0;
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CurOp++;
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if (HasVEX_4V) {
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VEX_4V = getVEXRegisterEncoding(MI, CurOp);
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if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
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EVEX_V2 = 0x0;
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CurOp++;
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}
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if (HasEVEX_K)
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EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);
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@ -1720,78 +1720,98 @@ defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem, memopv8i
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// AVX-512 Shift instructions
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//===----------------------------------------------------------------------===//
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multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
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string OpcodeStr,
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SDNode OpNode, RegisterClass RC, ValueType vt,
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X86MemOperand x86memop, PatFrag mem_frag> {
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string OpcodeStr, SDNode OpNode, RegisterClass RC,
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ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
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RegisterClass KRC> {
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def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
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(ins RC:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (vt (OpNode RC:$src1, (i32 imm:$src2))))],
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SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
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def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
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[], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
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def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
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(ins x86memop:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (OpNode (mem_frag addr:$src1),
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(i32 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
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def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
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(ins KRC:$mask, x86memop:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
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[], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
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}
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multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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RegisterClass RC, ValueType vt, ValueType SrcVT,
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PatFrag bc_frag> {
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PatFrag bc_frag, RegisterClass KRC> {
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// src2 is always 128-bit
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def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, VR128X:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
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SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
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def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, VR128X:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
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[], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
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def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (vt (OpNode RC:$src1,
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(bc_frag (memopv2i64 addr:$src2)))))],
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SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
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def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, RC:$src1, i128mem:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
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[], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
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}
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defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
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VR512, v16i32, i512mem, memopv16i32>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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VR512, v16i32, i512mem, memopv16i32, VK16WM>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
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VR512, v16i32, v4i32, bc_v4i32>, EVEX_V512,
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VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
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EVEX_CD8<32, CD8VQ>;
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defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
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VR512, v8i64, i512mem, memopv8i64>, EVEX_V512,
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VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
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EVEX_CD8<64, CD8VF>, VEX_W;
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defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
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VR512, v8i64, v2i64, bc_v2i64>, EVEX_V512,
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VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
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EVEX_CD8<64, CD8VQ>, VEX_W;
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defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
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VR512, v16i32, i512mem, memopv16i32>, EVEX_V512,
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VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
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VR512, v16i32, v4i32, bc_v4i32>, EVEX_V512,
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VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
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EVEX_CD8<32, CD8VQ>;
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defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
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VR512, v8i64, i512mem, memopv8i64>, EVEX_V512,
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VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
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EVEX_CD8<64, CD8VF>, VEX_W;
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defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
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VR512, v8i64, v2i64, bc_v2i64>, EVEX_V512,
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VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
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EVEX_CD8<64, CD8VQ>, VEX_W;
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defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
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VR512, v16i32, i512mem, memopv16i32>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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VR512, v16i32, i512mem, memopv16i32, VK16WM>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
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VR512, v16i32, v4i32, bc_v4i32>, EVEX_V512,
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VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
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EVEX_CD8<32, CD8VQ>;
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defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
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VR512, v8i64, i512mem, memopv8i64>, EVEX_V512,
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VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
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EVEX_CD8<64, CD8VF>, VEX_W;
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defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
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VR512, v8i64, v2i64, bc_v2i64>, EVEX_V512,
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VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
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EVEX_CD8<64, CD8VQ>, VEX_W;
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//===-------------------------------------------------------------------===//
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@ -818,17 +818,20 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
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case X86Local::MRM5r:
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case X86Local::MRM6r:
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case X86Local::MRM7r:
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// Operand 1 is a register operand in the R/M field.
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// Operand 2 (optional) is an immediate or relocation.
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// Operand 3 (optional) is an immediate.
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if (HasVEX_4VPrefix)
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assert(numPhysicalOperands <= 3 &&
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"Unexpected number of operands for MRMnRFrm with VEX_4V");
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else
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assert(numPhysicalOperands <= 3 &&
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"Unexpected number of operands for MRMnRFrm");
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{
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// Operand 1 is a register operand in the R/M field.
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// Operand 2 (optional) is an immediate or relocation.
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// Operand 3 (optional) is an immediate.
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unsigned kOp = (HasEVEX_K) ? 1:0;
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unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
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if (numPhysicalOperands > 3 + kOp + Op4v)
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llvm_unreachable("Unexpected number of operands for MRMnr");
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}
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if (HasVEX_4VPrefix)
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HANDLE_OPERAND(vvvvRegister)
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if (HasEVEX_K)
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HANDLE_OPERAND(writemaskRegister)
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HANDLE_OPTIONAL(rmRegister)
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HANDLE_OPTIONAL(relocation)
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HANDLE_OPTIONAL(immediate)
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@ -841,16 +844,19 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
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case X86Local::MRM5m:
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case X86Local::MRM6m:
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case X86Local::MRM7m:
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// Operand 1 is a memory operand (possibly SIB-extended)
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// Operand 2 (optional) is an immediate or relocation.
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if (HasVEX_4VPrefix)
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assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
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"Unexpected number of operands for MRMnMFrm");
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else
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assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
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"Unexpected number of operands for MRMnMFrm");
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{
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// Operand 1 is a memory operand (possibly SIB-extended)
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// Operand 2 (optional) is an immediate or relocation.
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unsigned kOp = (HasEVEX_K) ? 1:0;
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unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
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if (numPhysicalOperands < 1 + kOp + Op4v ||
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numPhysicalOperands > 2 + kOp + Op4v)
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llvm_unreachable("Unexpected number of operands for MRMnm");
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}
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if (HasVEX_4VPrefix)
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HANDLE_OPERAND(vvvvRegister)
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if (HasEVEX_K)
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HANDLE_OPERAND(writemaskRegister)
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HANDLE_OPERAND(memory)
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HANDLE_OPTIONAL(relocation)
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break;
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