From 1777d0c6c555fb20177b3a60b40eef265c2b842a Mon Sep 17 00:00:00 2001
From: Chris Lattner
Date: Tue, 5 May 2009 18:52:19 +0000
Subject: [PATCH] Add basic support for code generation of addrspace(257) -> FS
relative on x86. Patch by Zoltan Varga!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70992 91177308-0d34-0410-b5e6-96231b3b80d8
---
docs/CodeGenerator.html | 10 ++++++----
lib/Target/X86/X86Instr64bit.td | 5 +++++
lib/Target/X86/X86InstrInfo.td | 12 ++++++++++++
test/CodeGen/X86/movfs.ll | 8 ++++++++
4 files changed, 31 insertions(+), 4 deletions(-)
create mode 100644 test/CodeGen/X86/movfs.ll
diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html
index b4edbd73564..e620c1782e9 100644
--- a/docs/CodeGenerator.html
+++ b/docs/CodeGenerator.html
@@ -1844,11 +1844,13 @@ OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
segment. LLVM address space 0 is the default address space, which includes
the stack, and any unqualified memory accesses in a program. Address spaces
1-255 are currently reserved for user-defined code. The GS-segment is
- represented by address space 256. Other x86 segments have yet to be
- allocated address space numbers.
+ represented by address space 256, while the FS-segment is represented by
+ address space 257. Other x86 segments have yet to be allocated address space
+ numbers.
-Some operating systems use the GS-segment to implement TLS, so care should be
- taken when reading and writing to address space 256 on these platforms.
+Some operating systems use the FS/GS-segment to implement TLS, so care
+ should be taken when reading and writing to address space 256/257 on these
+ platforms.
diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td
index 715eb006e52..77847e474d0 100644
--- a/lib/Target/X86/X86Instr64bit.td
+++ b/lib/Target/X86/X86Instr64bit.td
@@ -1326,6 +1326,11 @@ def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"movq\t%gs:$src, $dst",
[(set GR64:$dst, (gsload addr:$src))]>, SegGS;
+let AddedComplexity = 5 in
+def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
+ "movq\t%fs:$src, $dst",
+ [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
+
//===----------------------------------------------------------------------===//
// Atomic Instructions
//===----------------------------------------------------------------------===//
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 33e0a3d67d2..0d3b6857e68 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -345,6 +345,13 @@ def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
return false;
}]>;
+def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
+ if (const Value *Src = cast(N)->getSrcValue())
+ if (const PointerType *PT = dyn_cast(Src->getType()))
+ return PT->getAddressSpace() == 257;
+ return false;
+}]>;
+
def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
if (const Value *Src = cast(N)->getSrcValue())
if (const PointerType *PT = dyn_cast(Src->getType()))
@@ -3004,6 +3011,11 @@ def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"movl\t%gs:$src, $dst",
[(set GR32:$dst, (gsload addr:$src))]>, SegGS;
+let AddedComplexity = 5 in
+def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
+ "movl\t%fs:$src, $dst",
+ [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
+
//===----------------------------------------------------------------------===//
// DWARF Pseudo Instructions
//
diff --git a/test/CodeGen/X86/movfs.ll b/test/CodeGen/X86/movfs.ll
new file mode 100644
index 00000000000..af102d49569
--- /dev/null
+++ b/test/CodeGen/X86/movfs.ll
@@ -0,0 +1,8 @@
+; RUN: llvm-as < %s | llc -march=x86 | grep fs
+
+define i32 @foo() nounwind readonly {
+entry:
+ %tmp = load i32* addrspace(257)* getelementptr (i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31) ; [#uses=1]
+ %tmp1 = load i32* %tmp ; [#uses=1]
+ ret i32 %tmp1
+}