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misched: Fix the DAG builder to handle an undef operand at ExitSU.

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Assertion failed: (VNI && "No value to read by operand")
rdar://12790267.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169071 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-12-01 01:22:44 +00:00
parent 30fe61aa35
commit 177d87ac8d
2 changed files with 28 additions and 1 deletions
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3
lib/CodeGen/ScheduleDAGInstrs.cpp
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@ -210,7 +210,8 @@ void ScheduleDAGInstrs::addSchedBarrierDeps() {
Uses[Reg].push_back(PhysRegSUOper(&ExitSU, -1));
else {
assert(!IsPostRA && "Virtual register encountered after regalloc.");
addVRegUseDeps(&ExitSU, i);
if (MO.readsReg()) // ignore undef operands
addVRegUseDeps(&ExitSU, i);
}
}
} else {

26
test/CodeGen/X86/misched-new.ll
View File

@ -51,3 +51,29 @@ if.end: ; preds = %if.then, %entry
}
declare void @bar(i32,i32)
; Test that the DAG builder can handle an undef vreg on ExitSU.
; CHECK: hasundef
; CHECK: call
%t0 = type { i32, i32, i8 }
%t6 = type { i32 (...)**, %t7* }
%t7 = type { i32 (...)** }
define void @hasundef() unnamed_addr uwtable ssp align 2 {
%1 = alloca %t0, align 8
br i1 undef, label %3, label %2
; <label>:2 ; preds = %0
unreachable
; <label>:3 ; preds = %0
br i1 undef, label %4, label %5
; <label>:4 ; preds = %3
call void undef(%t6* undef, %t0* %1)
unreachable
; <label>:5 ; preds = %3
ret void
}