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[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183613 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju
2013-06-08 15:32:59 +00:00
parent 9eefea009f
commit 1799921672
8 changed files with 108 additions and 162 deletions
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40
lib/Target/Sparc/SparcISelLowering.cpp
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@ -1315,6 +1315,12 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
// on SparcV8 and later.
setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
if (!Subtarget->isV9()) {
// SparcV8 does not have FNEGD and FABSD.
setOperationAction(ISD::FNEG, MVT::f64, Custom);
setOperationAction(ISD::FABS, MVT::f64, Custom);
}
setOperationAction(ISD::FSIN , MVT::f64, Expand);
setOperationAction(ISD::FCOS , MVT::f64, Expand);
setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
@ -1365,7 +1371,7 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
setStackPointerRegisterToSaveRestore(SP::O6);
if (TM.getSubtarget<SparcSubtarget>().isV9())
if (Subtarget->isV9())
setOperationAction(ISD::CTPOP, MVT::i32, Legal);
setMinFunctionAlignment(2);
@ -1751,10 +1757,42 @@ static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
return RetAddr;
}
static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG)
{
SDLoc dl(Op);
assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
assert(Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS);
// Lower fneg/fabs on f64 to fneg/fabs on f32.
// fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
// fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
SDValue SrcReg64 = Op.getOperand(0);
SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
SrcReg64);
SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
SrcReg64);
Hi32 = DAG.getNode(Op.getOpcode(), dl, MVT::f32, Hi32);
SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
dl, MVT::f64), 0);
DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
DstReg64, Hi32);
DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
DstReg64, Lo32);
return DstReg64;
}
SDValue SparcTargetLowering::
LowerOperation(SDValue Op, SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
default: llvm_unreachable("Should not custom lower this!");
case ISD::FNEG:
case ISD::FABS: return LowerF64Op(Op, DAG);
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
case ISD::GlobalTLSAddress: