6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-05 13:29:22 +00:00
Code Issues Projects Releases Wiki Activity

zap dead code.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113073 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-09-04 18:12:00 +00:00
parent 89f87e8f5a
commit 17aa68055b
18 changed files with 4 additions and 141 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Analysis/CFGPrinter.cpp
View File

@ -69,7 +69,6 @@ namespace {
struct CFGPrinter : public FunctionPass {
static char ID; // Pass identification, replacement for typeid
CFGPrinter() : FunctionPass(ID) {}
explicit CFGPrinter(char &pid) : FunctionPass(pid) {}
virtual bool runOnFunction(Function &F) {
std::string Filename = "cfg." + F.getNameStr() + ".dot";
@ -102,7 +101,6 @@ namespace {
struct CFGOnlyPrinter : public FunctionPass {
static char ID; // Pass identification, replacement for typeid
CFGOnlyPrinter() : FunctionPass(ID) {}
explicit CFGOnlyPrinter(char &pid) : FunctionPass(pid) {}
virtual bool runOnFunction(Function &F) {
std::string Filename = "cfg." + F.getNameStr() + ".dot";
errs() << "Writing '" << Filename << "'...";

4
lib/Analysis/LazyValueInfo.cpp
View File

@ -293,10 +293,6 @@ namespace {
void allUsesReplacedWith(Value* V) {
deleted();
}
LVIValueHandle &operator=(Value *V) {
return *this = LVIValueHandle(V, Parent);
}
};
/// ValueCache - This is all of the cached information for all values,

22
lib/Analysis/Lint.cpp
View File

@ -129,12 +129,6 @@ namespace {
}
}
void WriteType(const Type *T) {
if (!T) return;
MessagesStr << ' ';
WriteTypeSymbolic(MessagesStr, T, Mod);
}
// CheckFailed - A check failed, so print out the condition and the message
// that failed. This provides a nice place to put a breakpoint if you want
// to see why something is not correct.
@ -147,22 +141,6 @@ namespace {
WriteValue(V3);
WriteValue(V4);
}
void CheckFailed(const Twine &Message, const Value *V1,
const Type *T2, const Value *V3 = 0) {
MessagesStr << Message.str() << "\n";
WriteValue(V1);
WriteType(T2);
WriteValue(V3);
}
void CheckFailed(const Twine &Message, const Type *T1,
const Type *T2 = 0, const Type *T3 = 0) {
MessagesStr << Message.str() << "\n";
WriteType(T1);
WriteType(T2);
WriteType(T3);
}
};
}

1
lib/Analysis/LoopPass.cpp
View File

@ -30,7 +30,6 @@ private:
public:
static char ID;
PrintLoopPass() : LoopPass(ID), Out(dbgs()) {}
PrintLoopPass(const std::string &B, raw_ostream &o)
: LoopPass(ID), Banner(B), Out(o) {}

3
lib/Bitcode/Reader/BitcodeReader.cpp
View File

@ -136,7 +136,6 @@ namespace {
/// @brief A class for maintaining the slot number definition
/// as a placeholder for the actual definition for forward constants defs.
class ConstantPlaceHolder : public ConstantExpr {
ConstantPlaceHolder(); // DO NOT IMPLEMENT
void operator=(const ConstantPlaceHolder &); // DO NOT IMPLEMENT
public:
// allocate space for exactly one operand
@ -149,7 +148,7 @@ namespace {
}
/// @brief Methods to support type inquiry through isa, cast, and dyn_cast.
static inline bool classof(const ConstantPlaceHolder *) { return true; }
//static inline bool classof(const ConstantPlaceHolder *) { return true; }
static bool classof(const Value *V) {
return isa<ConstantExpr>(V) &&
cast<ConstantExpr>(V)->getOpcode() == Instruction::UserOp1;

1
lib/CodeGen/GCMetadata.cpp
View File

@ -30,7 +30,6 @@ namespace {
raw_ostream &OS;
public:
Printer() : FunctionPass(ID), OS(errs()) {}
explicit Printer(raw_ostream &OS) : FunctionPass(ID), OS(OS) {}

17
lib/CodeGen/MachineModuleInfo.cpp
View File

@ -562,20 +562,3 @@ unsigned MachineModuleInfo::getPersonalityIndex() const {
// in the zero index.
return 0;
}
namespace {
/// VariableDebugSorter - Comparison to sort the VariableDbgInfo map
/// by source location, to avoid depending on the arbitrary order that
/// instruction selection visits variables in.
struct VariableDebugSorter {
bool operator()(const MachineModuleInfo::VariableDbgInfoMapTy::value_type &A,
const MachineModuleInfo::VariableDbgInfoMapTy::value_type &B)
const {
if (A.second.second.getLine() != B.second.second.getLine())
return A.second.second.getLine() < B.second.second.getLine();
if (A.second.second.getCol() != B.second.second.getCol())
return A.second.second.getCol() < B.second.second.getCol();
return false;
}
};
}

4
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -160,10 +160,6 @@ namespace {
/// zero.
unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
unsigned Reloc);
unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
unsigned Reloc) {
return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc);
}
/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
///

13
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -130,19 +130,6 @@ namespace {
return (x - y) == r;
}
static bool isFPZ(SDValue N) {
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
return (CN && (CN->getValueAPF().isZero()));
}
static bool isFPZn(SDValue N) {
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
return (CN && CN->getValueAPF().isNegZero());
}
static bool isFPZp(SDValue N) {
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
return (CN && CN->getValueAPF().isPosZero());
}
public:
explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
: SelectionDAGISel(TM)

37
lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp
View File

@ -46,10 +46,6 @@ namespace {
return "STI CBEA SPU Assembly Printer";
}
SPUTargetMachine &getTM() {
return static_cast<SPUTargetMachine&>(TM);
}
/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
void printInstruction(const MachineInstr *MI, raw_ostream &OS);
@ -64,15 +60,6 @@ namespace {
}
void printOp(const MachineOperand &MO, raw_ostream &OS);
/// printRegister - Print register according to target requirements.
///
void printRegister(const MachineOperand &MO, bool R0AsZero, raw_ostream &O){
unsigned RegNo = MO.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(RegNo) &&
"Not physreg??");
O << getRegisterName(RegNo);
}
void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.isReg()) {
@ -92,17 +79,6 @@ namespace {
raw_ostream &O);
void
printS7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
{
int value = MI->getOperand(OpNo).getImm();
value = (value << (32 - 7)) >> (32 - 7);
assert((value >= -(1 << 8) && value <= (1 << 7) - 1)
&& "Invalid s7 argument");
O << value;
}
void
printU7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
{
@ -133,12 +109,6 @@ namespace {
O << (unsigned short)MI->getOperand(OpNo).getImm();
}
void
printU32ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O)
{
O << (unsigned)MI->getOperand(OpNo).getImm();
}
void
printMemRegReg(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
// When used as the base register, r0 reads constant zero rather than
@ -221,13 +191,6 @@ namespace {
printOp(MI->getOperand(OpNo), O);
}
void printHBROperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
// HBR operands are generated in front of branches, hence, the
// program counter plus the target.
O << ".+";
printOp(MI->getOperand(OpNo), O);
}
void printSymbolHi(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
if (MI->getOperand(OpNo).isImm()) {
printS16ImmOperand(MI, OpNo, O);

8
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -221,16 +221,10 @@ namespace {
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
inline SDValue getI64Imm(uint64_t Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i64);
}
/// getSmallIPtrImm - Return a target constant of pointer type.
inline SDValue getSmallIPtrImm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
}
}
SDNode *emitBuildVector(SDNode *bvNode) {
EVT vecVT = bvNode->getValueType(0);

9
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
View File

@ -60,15 +60,6 @@ namespace {
return GV != 0 || CP != 0 || ES != 0 || JT != -1;
}
bool hasBaseReg() const {
return Base.Reg.getNode() != 0;
}
void setBaseReg(SDValue Reg) {
BaseType = RegBase;
Base.Reg = Reg;
}
void dump() {
errs() << "MSP430ISelAddressMode " << this << '\n';
if (BaseType == RegBase && Base.Reg.getNode() != 0) {

4
lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp
View File

@ -67,10 +67,6 @@ namespace {
return "PowerPC Assembly Printer";
}
PPCTargetMachine &getTM() {
return static_cast<PPCTargetMachine&>(TM);
}
unsigned enumRegToMachineReg(unsigned enumReg) {
switch (enumReg) {
default: llvm_unreachable("Unhandled register!");

4
lib/Target/PowerPC/PPCCodeEmitter.cpp
View File

@ -67,10 +67,6 @@ namespace {
/// emitBasicBlock - emits the given MachineBasicBlock to memory
///
void emitBasicBlock(MachineBasicBlock &MBB);
/// getValueBit - return the particular bit of Val
///
unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; }
};
}

3
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -152,9 +152,6 @@ namespace {
return false;
}
SDValue BuildSDIVSequence(SDNode *N);
SDValue BuildUDIVSequence(SDNode *N);
void InsertVRSaveCode(MachineFunction &MF);
virtual const char *getPassName() const {

2
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -142,8 +142,6 @@ namespace {
bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
bool is12Bit, unsigned Depth = 0);
bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
bool MatchAddressRI(SDValue N, SystemZRRIAddressMode &AM,
bool is12Bit);
};
} // end anonymous namespace

6
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -264,12 +264,6 @@ namespace {
return CurDAG->getTargetConstant(Imm, MVT::i8);
}
/// getI16Imm - Return a target constant with the specified value, of type
/// i16.
inline SDValue getI16Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm, MVT::i16);
}
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDValue getI32Imm(unsigned Imm) {

5
lib/Transforms/Scalar/GVN.cpp
View File

@ -140,9 +140,9 @@ namespace {
}
}
bool operator!=(const Expression &other) const {
/*bool operator!=(const Expression &other) const {
return !(*this == other);
}
}*/
};
class ValueTable {
@ -176,7 +176,6 @@ namespace {
void add(Value *V, uint32_t num);
void clear();
void erase(Value *v);
unsigned size();
void setAliasAnalysis(AliasAnalysis* A) { AA = A; }
AliasAnalysis *getAliasAnalysis() const { return AA; }
void setMemDep(MemoryDependenceAnalysis* M) { MD = M; }