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https://github.com/c64scene-ar/llvm-6502.git
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AVX-512: Extend/Truncate operations for SKX,
SETCC for bit-vectors git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235875 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
c5889e0fab
commit
17bbdd05dd
@ -1303,6 +1303,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
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if (Subtarget->hasDQI()) {
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setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
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}
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setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
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@ -1313,7 +1317,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
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if (Subtarget->hasDQI()) {
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setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
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setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
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}
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setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
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setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
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setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
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@ -12055,6 +12062,23 @@ SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
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assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
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"Invalid TRUNCATE operation");
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// move vector to mask - truncate solution for SKX
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if (VT.getVectorElementType() == MVT::i1) {
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if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
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Subtarget->hasBWI())
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return Op; // legal, will go to VPMOVB2M, VPMOVW2M
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if ((InVT.is256BitVector() || InVT.is128BitVector())
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&& InVT.getScalarSizeInBits() <= 16 &&
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Subtarget->hasBWI() && Subtarget->hasVLX())
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return Op; // legal, will go to VPMOVB2M, VPMOVW2M
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if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
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Subtarget->hasDQI())
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return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
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if ((InVT.is256BitVector() || InVT.is128BitVector())
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&& InVT.getScalarSizeInBits() >= 32 &&
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Subtarget->hasDQI() && Subtarget->hasVLX())
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return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
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}
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if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
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if (VT.getVectorElementType().getSizeInBits() >=8)
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return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
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@ -13001,6 +13025,49 @@ static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
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DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
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}
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static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
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SDValue Op0 = Op.getOperand(0);
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SDValue Op1 = Op.getOperand(1);
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SDValue CC = Op.getOperand(2);
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MVT VT = Op.getSimpleValueType();
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SDLoc dl(Op);
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assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
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"Unexpected type for boolean compare operation");
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ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
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SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
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DAG.getConstant(-1, VT));
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SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
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DAG.getConstant(-1, VT));
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switch (SetCCOpcode) {
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default: llvm_unreachable("Unexpected SETCC condition");
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case ISD::SETNE:
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// (x != y) -> ~(x ^ y)
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return DAG.getNode(ISD::XOR, dl, VT,
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DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
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DAG.getConstant(-1, VT));
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case ISD::SETEQ:
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// (x == y) -> (x ^ y)
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return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
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case ISD::SETUGT:
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case ISD::SETGT:
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// (x > y) -> (x & ~y)
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return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
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case ISD::SETULT:
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case ISD::SETLT:
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// (x < y) -> (~x & y)
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return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
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case ISD::SETULE:
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case ISD::SETLE:
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// (x <= y) -> (~x | y)
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return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
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case ISD::SETUGE:
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case ISD::SETGE:
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// (x >=y) -> (x | ~y)
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return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
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}
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}
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static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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SDValue Op0 = Op.getOperand(0);
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@ -13119,8 +13186,11 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
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if (VT.is256BitVector() && !Subtarget->hasInt256())
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return Lower256IntVSETCC(Op, DAG);
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bool MaskResult = (VT.getVectorElementType() == MVT::i1);
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EVT OpVT = Op1.getValueType();
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if (OpVT.getVectorElementType() == MVT::i1)
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return LowerBoolVSETCC_AVX512(Op, DAG);
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bool MaskResult = (VT.getVectorElementType() == MVT::i1);
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if (Subtarget->hasAVX512()) {
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if (Op1.getValueType().is512BitVector() ||
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(Subtarget->hasBWI() && Subtarget->hasVLX()) ||
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@ -1906,18 +1906,21 @@ def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
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let Predicates = [HasAVX512, NoDQI] in {
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def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
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(COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
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def : Pat<(not VK8:$src),
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(COPY_TO_REGCLASS
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(KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
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}
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def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
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(COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
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def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
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(COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
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// Mask binary operation
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// - KAND, KANDN, KOR, KXNOR, KXOR
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multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
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RegisterClass KRC, SDPatternOperator OpNode,
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Predicate prd> {
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let Predicates = [prd] in
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Predicate prd, bit IsCommutable> {
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let Predicates = [prd], isCommutable = IsCommutable in
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def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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@ -1925,40 +1928,25 @@ multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
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}
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multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
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SDPatternOperator OpNode> {
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SDPatternOperator OpNode, bit IsCommutable> {
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defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
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HasDQI>, VEX_4V, VEX_L, PD;
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HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
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defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
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HasAVX512>, VEX_4V, VEX_L, PS;
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HasAVX512, IsCommutable>, VEX_4V, VEX_L, PS;
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defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
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HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
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HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
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defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
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HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
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HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
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}
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def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
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def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
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let isCommutable = 1 in {
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defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
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defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
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defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
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defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
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}
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let isCommutable = 0 in
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defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
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def : Pat<(xor VK1:$src1, VK1:$src2),
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(COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
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(COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
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def : Pat<(or VK1:$src1, VK1:$src2),
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(COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
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(COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
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def : Pat<(and VK1:$src1, VK1:$src2),
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(COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
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(COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
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defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
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defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
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defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
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defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
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defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
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multiclass avx512_mask_binop_int<string IntName, string InstName> {
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let Predicates = [HasAVX512] in
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@ -1975,13 +1963,28 @@ defm : avx512_mask_binop_int<"kor", "KOR">;
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defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
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defm : avx512_mask_binop_int<"kxor", "KXOR">;
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// With AVX-512, 8-bit mask is promoted to 16-bit mask.
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multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
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let Predicates = [HasAVX512] in
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def : Pat<(OpNode VK8:$src1, VK8:$src2),
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(COPY_TO_REGCLASS
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(Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
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(COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
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// With AVX512F, 8-bit mask is promoted to 16-bit mask,
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// for the DQI set, this type is legal and KxxxB instruction is used
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let Predicates = [NoDQI] in
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def : Pat<(OpNode VK8:$src1, VK8:$src2),
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(COPY_TO_REGCLASS
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(Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
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(COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
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// All types smaller than 8 bits require conversion anyway
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def : Pat<(OpNode VK1:$src1, VK1:$src2),
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(COPY_TO_REGCLASS (Inst
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(COPY_TO_REGCLASS VK1:$src1, VK16),
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(COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
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def : Pat<(OpNode VK2:$src1, VK2:$src2),
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(COPY_TO_REGCLASS (Inst
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(COPY_TO_REGCLASS VK2:$src1, VK16),
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(COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
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def : Pat<(OpNode VK4:$src1, VK4:$src2),
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(COPY_TO_REGCLASS (Inst
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(COPY_TO_REGCLASS VK4:$src1, VK16),
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(COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
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}
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defm : avx512_binop_pat<and, KANDWrr>;
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@ -1990,6 +1993,32 @@ defm : avx512_binop_pat<or, KORWrr>;
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defm : avx512_binop_pat<xnor, KXNORWrr>;
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defm : avx512_binop_pat<xor, KXORWrr>;
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def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
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(KXNORWrr VK16:$src1, VK16:$src2)>;
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def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
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(KXNORBrr VK8:$src1, VK8:$src2)>;
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def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
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(KXNORDrr VK32:$src1, VK32:$src2)>;
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def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
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(KXNORQrr VK64:$src1, VK64:$src2)>;
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let Predicates = [NoDQI] in
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def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
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(COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
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(COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
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def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
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(COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
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(COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
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def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
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(COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
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(COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
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def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
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(COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
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(COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
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// Mask unpacking
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multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
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RegisterClass KRC> {
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@ -2085,6 +2114,8 @@ multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
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multiclass avx512_mask_setop_w<PatFrag Val> {
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defm B : avx512_mask_setop<VK8, v8i1, Val>;
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defm W : avx512_mask_setop<VK16, v16i1, Val>;
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defm D : avx512_mask_setop<VK32, v32i1, Val>;
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defm Q : avx512_mask_setop<VK64, v64i1, Val>;
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}
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defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
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@ -2094,6 +2125,8 @@ defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
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let Predicates = [HasAVX512] in {
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def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
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def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
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def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
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def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
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def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
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def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
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def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
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@ -131,4 +131,30 @@ entry:
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%mask = load <8 x i1>, <8 x i1>* %maskPtr
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%mask_convert = bitcast <8 x i1> %mask to i8
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ret i8 %mask_convert
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}
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; SKX-LABEL: test4
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; SKX: vpcmpgt
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; SKX: knot
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; SKX: vpcmpgt
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; SKX: vpmovm2d
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define <4 x i32> @test4(<4 x i64> %x, <4 x i64> %y, <4 x i64> %x1, <4 x i64> %y1) {
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%x_gt_y = icmp sgt <4 x i64> %x, %y
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%x1_gt_y1 = icmp sgt <4 x i64> %x1, %y1
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%res = icmp sgt <4 x i1>%x_gt_y, %x1_gt_y1
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%resse = sext <4 x i1>%res to <4 x i32>
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ret <4 x i32> %resse
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}
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; SKX-LABEL: test5
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; SKX: vpcmpgt
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; SKX: knot
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; SKX: vpcmpgt
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; SKX: vpmovm2q
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define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y, <2 x i64> %x1, <2 x i64> %y1) {
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%x_gt_y = icmp slt <2 x i64> %x, %y
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%x1_gt_y1 = icmp sgt <2 x i64> %x1, %y1
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%res = icmp slt <2 x i1>%x_gt_y, %x1_gt_y1
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%resse = sext <2 x i1>%res to <2 x i64>
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ret <2 x i64> %resse
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}
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@ -90,6 +90,8 @@ define <8 x i64> @zext_8i1_to_8xi64(i8 %b) {
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; CHECK: vpandd
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; CHECK: vptestmd
|
||||
; CHECK: ret
|
||||
; SKX-LABEL: trunc_16i8_to_16i1
|
||||
; SKX: vpmovb2m %xmm
|
||||
define i16 @trunc_16i8_to_16i1(<16 x i8> %a) {
|
||||
%mask_b = trunc <16 x i8>%a to <16 x i1>
|
||||
%mask = bitcast <16 x i1> %mask_b to i16
|
||||
@ -100,17 +102,34 @@ define i16 @trunc_16i8_to_16i1(<16 x i8> %a) {
|
||||
; CHECK: vpandd
|
||||
; CHECK: vptestmd
|
||||
; CHECK: ret
|
||||
; SKX-LABEL: trunc_16i32_to_16i1
|
||||
; SKX: vpmovd2m %zmm
|
||||
define i16 @trunc_16i32_to_16i1(<16 x i32> %a) {
|
||||
%mask_b = trunc <16 x i32>%a to <16 x i1>
|
||||
%mask = bitcast <16 x i1> %mask_b to i16
|
||||
ret i16 %mask
|
||||
}
|
||||
|
||||
; SKX-LABEL: trunc_4i32_to_4i1
|
||||
; SKX: vpmovd2m %xmm
|
||||
; SKX: kandw
|
||||
; SKX: vpmovm2d
|
||||
define <4 x i32> @trunc_4i32_to_4i1(<4 x i32> %a, <4 x i32> %b) {
|
||||
%mask_a = trunc <4 x i32>%a to <4 x i1>
|
||||
%mask_b = trunc <4 x i32>%b to <4 x i1>
|
||||
%a_and_b = and <4 x i1>%mask_a, %mask_b
|
||||
%res = sext <4 x i1>%a_and_b to <4 x i32>
|
||||
ret <4 x i32>%res
|
||||
}
|
||||
|
||||
; CHECK-LABEL: trunc_8i16_to_8i1
|
||||
; CHECK: vpmovsxwq
|
||||
; CHECK: vpandq LCP{{.*}}(%rip){1to8}
|
||||
; CHECK: vptestmq
|
||||
; CHECK: ret
|
||||
|
||||
; SKX-LABEL: trunc_8i16_to_8i1
|
||||
; SKX: vpmovw2m %xmm
|
||||
define i8 @trunc_8i16_to_8i1(<8 x i16> %a) {
|
||||
%mask_b = trunc <8 x i16>%a to <8 x i1>
|
||||
%mask = bitcast <8 x i1> %mask_b to i8
|
||||
|
||||
@ -374,3 +374,27 @@ define <8 x i64> @test27(<8 x i64> %x, i64* %yb.ptr, <8 x i64> %x1, <8 x i64> %y
|
||||
%max = select <8 x i1> %mask, <8 x i64> %x, <8 x i64> %x1
|
||||
ret <8 x i64> %max
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test28
|
||||
; CHECK: vpcmpgtq
|
||||
; CHECK: vpcmpgtq
|
||||
; CHECK: kxorw
|
||||
define <8 x i32>@test28(<8 x i64> %x, <8 x i64> %y, <8 x i64> %x1, <8 x i64> %y1) {
|
||||
%x_gt_y = icmp sgt <8 x i64> %x, %y
|
||||
%x1_gt_y1 = icmp sgt <8 x i64> %x1, %y1
|
||||
%res = icmp eq <8 x i1>%x_gt_y, %x1_gt_y1
|
||||
%resse = sext <8 x i1>%res to <8 x i32>
|
||||
ret <8 x i32> %resse
|
||||
}
|
||||
|
||||
; CHECK-LABEL: test29
|
||||
; CHECK: vpcmpgtd
|
||||
; CHECK: vpcmpgtd
|
||||
; CHECK: kxnorw
|
||||
define <16 x i8>@test29(<16 x i32> %x, <16 x i32> %y, <16 x i32> %x1, <16 x i32> %y1) {
|
||||
%x_gt_y = icmp sgt <16 x i32> %x, %y
|
||||
%x1_gt_y1 = icmp sgt <16 x i32> %x1, %y1
|
||||
%res = icmp ne <16 x i1>%x_gt_y, %x1_gt_y1
|
||||
%resse = sext <16 x i1>%res to <16 x i8>
|
||||
ret <16 x i8> %resse
|
||||
}
|
||||
Loading…
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Reference in New Issue
Block a user