From 17c1e51d223c8f5ac2446b37495e0aa124dedbe9 Mon Sep 17 00:00:00 2001 From: Richard Osborne Date: Thu, 3 Feb 2011 13:14:25 +0000 Subject: [PATCH] Add XCore intrinsics for resource instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124794 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/IntrinsicsXCore.td | 20 ++++++ lib/Target/XCore/XCoreInstrInfo.td | 55 +++++++++++++++-- test/CodeGen/XCore/resources.ll | 97 ++++++++++++++++++++++++++++++ 3 files changed, 168 insertions(+), 4 deletions(-) create mode 100644 test/CodeGen/XCore/resources.ll diff --git a/include/llvm/IntrinsicsXCore.td b/include/llvm/IntrinsicsXCore.td index a86cda28a5e..1222650608a 100644 --- a/include/llvm/IntrinsicsXCore.td +++ b/include/llvm/IntrinsicsXCore.td @@ -11,4 +11,24 @@ let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.". def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>; def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>; + + // Resource instructions. + def int_xcore_getr : Intrinsic<[llvm_anyptr_ty],[llvm_i32_ty]>; + def int_xcore_freer : Intrinsic<[],[llvm_anyptr_ty], + [NoCapture<0>]>; + def int_xcore_in : Intrinsic<[llvm_i32_ty],[llvm_anyptr_ty],[NoCapture<0>]>; + def int_xcore_int : Intrinsic<[llvm_i32_ty],[llvm_anyptr_ty], + [NoCapture<0>]>; + def int_xcore_inct : Intrinsic<[llvm_i32_ty],[llvm_anyptr_ty], + [NoCapture<0>]>; + def int_xcore_out : Intrinsic<[],[llvm_anyptr_ty, llvm_i32_ty], + [NoCapture<0>]>; + def int_xcore_outt : Intrinsic<[],[llvm_anyptr_ty, llvm_i32_ty], + [NoCapture<0>]>; + def int_xcore_outct : Intrinsic<[],[llvm_anyptr_ty, llvm_i32_ty], + [NoCapture<0>]>; + def int_xcore_chkct : Intrinsic<[],[llvm_anyptr_ty, llvm_i32_ty], + [NoCapture<0>]>; + def int_xcore_setd : Intrinsic<[],[llvm_anyptr_ty, llvm_i32_ty], + [NoCapture<0>]>; } diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index 14ccf1325f9..581f38475a3 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -720,9 +720,8 @@ def NEG : _F2R<(outs GRRegs:$dst), (ins GRRegs:$b), "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>; -// TODO setd, eet, eef, getts, setpt, outct, inct, chkct, outt, intt, out, -// in, outshr, inshr, testct, testwct, tinitpc, tinitdp, tinitsp, tinitcp, -// tsetmr, sext (reg), zext (reg) +// TODO setd, eet, eef, getts, setpt, outshr, inshr, testwct, tinitpc, tinitdp, +// tinitsp, tinitcp, tsetmr, sext (reg), zext (reg) let Constraints = "$src1 = $dst" in { let neverHasSideEffects = 1 in def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), @@ -748,6 +747,50 @@ def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size), "mkmsk $dst, $size", [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), 0xffffffff))]>; +def GETR_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$type), + "getr $dst, $type", + [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>; + +def OUTCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), + "outct res[$r], $val", + [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>; + +def OUTCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val), + "outct res[$r], $val", + [(int_xcore_outct GRRegs:$r, immUs:$val)]>; + +def OUTT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), + "outt res[$r], $val", + [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>; + +def OUT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), + "out res[$r], $val", + [(int_xcore_out GRRegs:$r, GRRegs:$val)]>; + +def INCT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), + "inct $dst, res[$r]", + [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>; + +def INT_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), + "int $dst, res[$r]", + [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>; + +def IN_2r : _F2R<(outs GRRegs:$dst), (ins GRRegs:$r), + "in $dst, res[$r]", + [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>; + +def CHKCT_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), + "chkct res[$r], $val", + [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>; + +def CHKCT_rus : _F2R<(outs), (ins GRRegs:$r, i32imm:$val), + "chkct res[$r], $val", + [(int_xcore_chkct GRRegs:$r, immUs:$val)]>; + +def SETD_2r : _F2R<(outs), (ins GRRegs:$r, GRRegs:$val), + "setd res[$r], $val", + [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>; + // Two operand long // TODO settw, setclk, setrdy, setpsc, endin, peek, // getd, testlcl, tinitlr, getps, setps @@ -764,7 +807,7 @@ def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; // One operand short -// TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp +// TODO edu, eeu, waitet, waitef, tstart, msync, mjoin, syncr, clrtp // setdp, setcp, setv, setev, kcall // dgetreg let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in @@ -805,6 +848,10 @@ def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops), [(XCoreBranchLink GRRegs:$addr)]>; } +def FREER_1r : _F1R<(outs), (ins GRRegs:$r), + "freer res[$r]", + [(int_xcore_freer GRRegs:$r)]>; + // Zero operand short // TODO waiteu, clre, ssync, freet, ldspc, stspc, ldssr, stssr, ldsed, stsed, // stet, geted, getet, getkep, getksp, setkep, getid, kret, dcall, dret, diff --git a/test/CodeGen/XCore/resources.ll b/test/CodeGen/XCore/resources.ll new file mode 100644 index 00000000000..878f3183ca0 --- /dev/null +++ b/test/CodeGen/XCore/resources.ll @@ -0,0 +1,97 @@ +; RUN: llc -march=xcore < %s | FileCheck %s + +declare i8 addrspace(1)* @llvm.xcore.getr.p1i8(i32 %type) +declare void @llvm.xcore.freer.p1i8(i8 addrspace(1)* %r) +declare i32 @llvm.xcore.in.p1i8(i8 addrspace(1)* %r) +declare i32 @llvm.xcore.int.p1i8(i8 addrspace(1)* %r) +declare i32 @llvm.xcore.inct.p1i8(i8 addrspace(1)* %r) +declare void @llvm.xcore.out.p1i8(i8 addrspace(1)* %r, i32 %value) +declare void @llvm.xcore.outt.p1i8(i8 addrspace(1)* %r, i32 %value) +declare void @llvm.xcore.outct.p1i8(i8 addrspace(1)* %r, i32 %value) +declare void @llvm.xcore.chkct.p1i8(i8 addrspace(1)* %r, i32 %value) +declare void @llvm.xcore.setd.p1i8(i8 addrspace(1)* %r, i32 %value) +declare void @llvm.xcore.setc.p1i8(i8 addrspace(1)* %r, i32 %value) + +define i8 addrspace(1)* @getr() { +; CHECK: getr: +; CHECK: getr r0, 5 + %result = call i8 addrspace(1)* @llvm.xcore.getr.p1i8(i32 5) + ret i8 addrspace(1)* %result +} + +define void @freer(i8 addrspace(1)* %r) { +; CHECK: freer: +; CHECK: freer res[r0] + call void @llvm.xcore.freer.p1i8(i8 addrspace(1)* %r) + ret void +} + +define i32 @in(i8 addrspace(1)* %r) { +; CHECK: in: +; CHECK: in r0, res[r0] + %result = call i32 @llvm.xcore.in.p1i8(i8 addrspace(1)* %r) + ret i32 %result +} + +define i32 @int(i8 addrspace(1)* %r) { +; CHECK: int: +; CHECK: int r0, res[r0] + %result = call i32 @llvm.xcore.int.p1i8(i8 addrspace(1)* %r) + ret i32 %result +} + +define i32 @inct(i8 addrspace(1)* %r) { +; CHECK: inct: +; CHECK: inct r0, res[r0] + %result = call i32 @llvm.xcore.inct.p1i8(i8 addrspace(1)* %r) + ret i32 %result +} + +define void @out(i8 addrspace(1)* %r, i32 %value) { +; CHECK: out: +; CHECK: out res[r0], r1 + call void @llvm.xcore.out.p1i8(i8 addrspace(1)* %r, i32 %value) + ret void +} + +define void @outt(i8 addrspace(1)* %r, i32 %value) { +; CHECK: outt: +; CHECK: outt res[r0], r1 + call void @llvm.xcore.outt.p1i8(i8 addrspace(1)* %r, i32 %value) + ret void +} + +define void @outct(i8 addrspace(1)* %r, i32 %value) { +; CHECK: outct: +; CHECK: outct res[r0], r1 + call void @llvm.xcore.outct.p1i8(i8 addrspace(1)* %r, i32 %value) + ret void +} + +define void @outcti(i8 addrspace(1)* %r) { +; CHECK: outcti: +; CHECK: outct res[r0], 11 + call void @llvm.xcore.outct.p1i8(i8 addrspace(1)* %r, i32 11) + ret void +} + +define void @chkct(i8 addrspace(1)* %r, i32 %value) { +; CHECK: chkct: +; CHECK: chkct res[r0], r1 + call void @llvm.xcore.chkct.p1i8(i8 addrspace(1)* %r, i32 %value) + ret void +} + +define void @chkcti(i8 addrspace(1)* %r) { +; CHECK: chkcti: +; CHECK: chkct res[r0], 11 + call void @llvm.xcore.chkct.p1i8(i8 addrspace(1)* %r, i32 11) + ret void +} + +define void @setd(i8 addrspace(1)* %r, i32 %value) { +; CHECK: setd: +; CHECK: setd res[r0], r1 + call void @llvm.xcore.setd.p1i8(i8 addrspace(1)* %r, i32 %value) + ret void +}