add support for encoding the lo14 forms used for a few PPC64 addressing

modes.  For example, we now get:

	ld r3, lo16(_G)(r3)             ; encoding: [0xe8,0x63,A,0bAAAAAA00]
                                        ;   fixup A - offset: 0, value: lo16(_G), kind: fixup_ppc_lo14



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119133 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2010-11-15 08:02:41 +00:00
parent f3b6e06679
commit 17e2c18835
5 changed files with 45 additions and 25 deletions
+11 -12
View File
@@ -66,7 +66,7 @@ namespace {
unsigned getHA16Encoding(const MachineInstr &MI, unsigned OpNo) const;
unsigned getLO16Encoding(const MachineInstr &MI, unsigned OpNo) const;
unsigned getLO14Encoding(const MachineInstr &MI, unsigned OpNo) const;
unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
@@ -209,13 +209,19 @@ unsigned PPCCodeEmitter::getLO16Encoding(const MachineInstr &MI,
return 0;
}
unsigned PPCCodeEmitter::getLO14Encoding(const MachineInstr &MI,
unsigned OpNo) const {
unsigned PPCCodeEmitter::getMemRIXEncoding(const MachineInstr &MI,
unsigned OpNo) const {
// Encode (imm, reg) as a memrix, which has the low 14-bits as the
// displacement and the next 5 bits as the register #.
assert(MI.getOperand(OpNo+1).isReg());
unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14;
const MachineOperand &MO = MI.getOperand(OpNo);
if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
if (MO.isImm())
return (getMachineOpValue(MI, MO) & 0x3FFF) | RegBits;
MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low_ix));
return 0;
return RegBits;
}
@@ -259,13 +265,6 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
case PPC::STFD:
Reloc = PPC::reloc_absolute_low;
break;
case PPC::LWA:
case PPC::LD:
case PPC::STD:
case PPC::STD_32:
Reloc = PPC::reloc_absolute_low_ix;
break;
}
MCE.addRelocation(GetRelocation(MO, Reloc));