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Revert r221056 and others, "[mips] Move F128 argument handling into MipsCCState as we did for returns. NFC."
r221056 "[mips] Move F128 argument handling into MipsCCState as we did for returns. NFC." r221058 "[mips] Fix unused variable warning introduced in r221056" r221059 "[mips] Move all ByVal handling into CCState and tablegen-erated code. NFC." r221061 "Renamed CCState members that appear to misspell 'Processed' as 'Proceed'. NFC." It cuased an undefined behavior in LLVM :: CodeGen/Mips/return-vector.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221081 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -21,7 +21,6 @@ add_llvm_target(MipsCodeGen
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Mips16ISelDAGToDAG.cpp
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Mips16ISelLowering.cpp
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Mips16RegisterInfo.cpp
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MipsABIInfo.cpp
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MipsAnalyzeImmediate.cpp
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MipsAsmPrinter.cpp
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MipsConstantIslandPass.cpp
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@ -244,9 +244,10 @@ Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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}
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}
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bool Mips16TargetLowering::isEligibleForTailCallOptimization(
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const CCState &CCInfo, unsigned NextStackOffset,
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const MipsFunctionInfo &FI) const {
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bool Mips16TargetLowering::
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isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
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unsigned NextStackOffset,
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const MipsFunctionInfo& FI) const {
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// No tail call optimization for mips16.
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return false;
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}
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@ -31,9 +31,9 @@ namespace llvm {
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MachineBasicBlock *MBB) const override;
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private:
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bool isEligibleForTailCallOptimization(
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const CCState &CCInfo, unsigned NextStackOffset,
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const MipsFunctionInfo &FI) const override;
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bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
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unsigned NextStackOffset,
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const MipsFunctionInfo& FI) const override;
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void setMips16HardFloatLibCalls();
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@ -1,29 +0,0 @@
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//===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsABIInfo.h"
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#include "MipsRegisterInfo.h"
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using namespace llvm;
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namespace {
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static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
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static const MCPhysReg Mips64IntRegs[8] = {
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Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
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Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
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}
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const ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const {
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if (IsO32())
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return makeArrayRef(O32IntRegs);
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if (IsN32() || IsN64())
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return makeArrayRef(Mips64IntRegs);
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llvm_unreachable("Unhandled ABI");
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}
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@ -10,11 +10,7 @@
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#ifndef MIPSABIINFO_H
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#define MIPSABIINFO_H
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/MC/MCRegisterInfo.h"
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namespace llvm {
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class MipsABIInfo {
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public:
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enum class ABI { Unknown, O32, N32, N64, EABI };
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@ -38,8 +34,6 @@ public:
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bool IsEABI() const { return ThisABI == ABI::EABI; }
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ABI GetEnumValue() const { return ThisABI; }
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const ArrayRef<MCPhysReg> GetByValArgRegs() const;
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/// Ordering of ABI's
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/// MipsGenSubtargetInfo.inc will use this to resolve conflicts when given
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/// multiple ABI options.
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@ -279,6 +279,13 @@ def CC_Mips_FastCC : CallingConv<[
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CCDelegateTo<CC_MipsN_FastCC>
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]>;
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//==
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def CC_Mips16RetHelper : CallingConv<[
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// Integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
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]>;
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//===----------------------------------------------------------------------===//
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// Mips Calling Convention Dispatch
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//===----------------------------------------------------------------------===//
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@ -290,29 +297,7 @@ def RetCC_Mips : CallingConv<[
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CCDelegateTo<RetCC_MipsO32>
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]>;
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def CC_Mips_ByVal : CallingConv<[
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CCIfSubtarget<"isABI_O32()", CCIfByVal<CCPassByVal<4, 4>>>,
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CCIfByVal<CCPassByVal<8, 8>>
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]>;
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def CC_Mips_FixedArg : CallingConv<[
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CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
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// f128 needs to be handled similarly to f32 and f64 on hard-float. However,
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// f128 is not legal and is lowered to i128 which is further lowered to a pair
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// of i64's.
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// This presents us with a problem for the calling convention since hard-float
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// still needs to pass them in FPU registers. We therefore resort to a
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// pre-analyze (see PreAnalyzeFormalArgsForF128()) step to pass information on
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// whether the argument was originally an f128 into the tablegen-erated code.
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//
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// f128 should only occur for the N64 ABI where long double is 128-bit. On
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// N32, long double is equivalent to double.
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CCIfType<[i64],
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CCIfSubtargetNot<"abiUsesSoftFloat()",
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CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)",
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CCBitConvertToType<f64>>>>,
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CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>,
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// FIXME: There wasn't an EABI case in the original code and it seems unlikely
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@ -322,23 +307,12 @@ def CC_Mips_FixedArg : CallingConv<[
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]>;
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def CC_Mips_VarArg : CallingConv<[
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CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
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// FIXME: There wasn't an EABI case in the original code and it seems unlikely
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// that it's the same as CC_MipsN_VarArg
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CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
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CCDelegateTo<CC_MipsN_VarArg>
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]>;
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//==
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def CC_Mips16RetHelper : CallingConv<[
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CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
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// Integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
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]>;
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//===----------------------------------------------------------------------===//
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// Callee-saved register lists.
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//===----------------------------------------------------------------------===//
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@ -95,51 +95,10 @@ private:
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originalTypeIsF128(MF.getFunction()->getReturnType(), nullptr));
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}
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/// Identify lowered values that originated from f128 arguments and record
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/// this.
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void PreAnalyzeCallOperandsForF128(
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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std::vector<TargetLowering::ArgListEntry> &FuncArgs, SDNode *CallNode) {
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for (unsigned i = 0; i < Outs.size(); ++i)
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OriginalArgWasF128.push_back(
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originalTypeIsF128(FuncArgs[Outs[i].OrigArgIndex].Ty, CallNode));
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}
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/// Identify lowered values that originated from f128 arguments and record
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/// this.
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void
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PreAnalyzeFormalArgumentsForF128(const SmallVectorImpl<ISD::InputArg> &Ins) {
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const MachineFunction &MF = getMachineFunction();
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for (unsigned i = 0; i < Ins.size(); ++i) {
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Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
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std::advance(FuncArg, Ins[i].OrigArgIndex);
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OriginalArgWasF128.push_back(
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originalTypeIsF128(FuncArg->getType(), nullptr));
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}
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}
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/// Records whether the value has been lowered from an f128.
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SmallVector<bool, 4> OriginalArgWasF128;
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public:
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// FIXME: Remove this from a public inteface ASAP. It's a temporary trap door
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// to allow analyzeCallOperands to be removed incrementally.
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void PreAnalyzeCallOperandsForF128_(
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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std::vector<TargetLowering::ArgListEntry> &FuncArgs, SDNode *CallNode) {
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PreAnalyzeCallOperandsForF128(Outs, FuncArgs, CallNode);
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}
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// FIXME: Remove this from a public inteface ASAP. It's a temporary trap door
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// to allow analyzeFormalArguments to be removed incrementally.
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void
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PreAnalyzeFormalArgumentsForF128_(const SmallVectorImpl<ISD::InputArg> &Ins) {
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PreAnalyzeFormalArgumentsForF128(Ins);
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}
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// FIXME: Remove this from a public inteface ASAP. It's a temporary trap door
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// to clean up after the above functions.
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void ClearOriginalArgWasF128() { OriginalArgWasF128.clear(); }
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MipsCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
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SmallVectorImpl<CCValAssign> &locs, LLVMContext &C)
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: CCState(CC, isVarArg, MF, locs, C) {}
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@ -2587,22 +2546,21 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
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*DAG.getContext());
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CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
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*DAG.getContext());
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MipsCC MipsCCInfo(CallConv, Subtarget, CCInfo);
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CCInfo.PreAnalyzeCallOperandsForF128_(Outs, CLI.getArgs(), Callee.getNode());
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MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, Subtarget.abiUsesSoftFloat(),
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Callee.getNode(), CLI.getArgs(), CCInfo);
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CCInfo.ClearOriginalArgWasF128();
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NextStackOffset = CCInfo.getNextStackOffset();
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// Check if it's really possible to do a tail call.
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if (IsTailCall)
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IsTailCall = isEligibleForTailCallOptimization(
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CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
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IsTailCall =
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isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset,
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*MF.getInfo<MipsFunctionInfo>());
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if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
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report_fatal_error("failed to perform tail call elimination on a call "
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@ -2628,8 +2586,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// With EABI is it possible to have 16 args on registers.
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std::deque< std::pair<unsigned, SDValue> > RegsToPass;
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SmallVector<SDValue, 8> MemOpChains;
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CCInfo.rewindByValRegsInfo();
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MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
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// Walk the register/memloc assignments, inserting copies/loads.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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@ -2640,19 +2597,14 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// ByVal Arg.
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if (Flags.isByVal()) {
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unsigned FirstByValReg, LastByValReg;
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unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
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CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
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assert(Flags.getByValSize() &&
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"ByVal args of size 0 should have been ignored by front-end.");
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assert(ByValIdx < CCInfo.getInRegsParamsCount());
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assert(ByValArg != MipsCCInfo.byval_end());
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assert(!IsTailCall &&
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"Do not tail-call optimize if there is a byval argument.");
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passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
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MipsCCInfo, FirstByValReg, LastByValReg, Flags,
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Subtarget.isLittle(), VA);
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CCInfo.nextInRegsParam();
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MipsCCInfo, *ByValArg, Flags, Subtarget.isLittle(), VA);
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++ByValArg;
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continue;
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}
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@ -2680,9 +2632,6 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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}
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}
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break;
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case CCValAssign::BCvt:
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Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
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break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
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break;
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@ -2880,21 +2829,19 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
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*DAG.getContext());
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CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
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*DAG.getContext());
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MipsCC MipsCCInfo(CallConv, Subtarget, CCInfo);
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Function::const_arg_iterator FuncArg =
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DAG.getMachineFunction().getFunction()->arg_begin();
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bool UseSoftFloat = Subtarget.abiUsesSoftFloat();
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CCInfo.PreAnalyzeFormalArgumentsForF128_(Ins);
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MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, CCInfo);
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CCInfo.ClearOriginalArgWasF128();
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MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg, CCInfo);
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MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
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CCInfo.getInRegsParamsCount() > 0);
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MipsCCInfo.hasByValArg());
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unsigned CurArgIdx = 0;
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CCInfo.rewindByValRegsInfo();
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MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin();
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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@ -2905,16 +2852,12 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
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bool IsRegLoc = VA.isRegLoc();
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if (Flags.isByVal()) {
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unsigned FirstByValReg, LastByValReg;
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unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
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CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
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assert(Flags.getByValSize() &&
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"ByVal args of size 0 should have been ignored by front-end.");
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assert(ByValIdx < CCInfo.getInRegsParamsCount());
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assert(ByValArg != MipsCCInfo.byval_end());
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copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
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MipsCCInfo, FirstByValReg, LastByValReg, VA);
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CCInfo.nextInRegsParam();
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MipsCCInfo, *ByValArg, VA);
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++ByValArg;
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continue;
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}
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@ -2932,24 +2875,16 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
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// If this is an 8 or 16-bit value, it has been passed promoted
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// to 32 bits. Insert an assert[sz]ext to capture this, then
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// truncate to the right size.
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switch (VA.getLocInfo()) {
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default:
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llvm_unreachable("Unknown loc info!");
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case CCValAssign::Full:
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break;
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case CCValAssign::SExt:
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ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
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DAG.getValueType(ValVT));
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if (VA.getLocInfo() != CCValAssign::Full) {
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unsigned Opcode = 0;
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if (VA.getLocInfo() == CCValAssign::SExt)
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Opcode = ISD::AssertSext;
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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Opcode = ISD::AssertZext;
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if (Opcode)
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ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue,
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DAG.getValueType(ValVT));
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ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue);
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break;
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case CCValAssign::ZExt:
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ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
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DAG.getValueType(ValVT));
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ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue);
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break;
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case CCValAssign::BCvt:
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ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
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break;
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}
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// Handle floating point arguments passed in integer registers and
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@ -3621,10 +3556,18 @@ void MipsTargetLowering::MipsCC::analyzeCallOperands(
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ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
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bool R;
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if (ArgFlags.isByVal()) {
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handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, State);
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continue;
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}
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if (IsVarArg && !Args[I].IsFixed)
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R = CC_Mips_VarArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, State);
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else
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R = FixedFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, State);
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else {
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MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode,
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IsSoftFloat);
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R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, State);
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}
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if (R) {
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#ifndef NDEBUG
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@ -3638,14 +3581,24 @@ void MipsTargetLowering::MipsCC::analyzeCallOperands(
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void MipsTargetLowering::MipsCC::analyzeFormalArguments(
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const SmallVectorImpl<ISD::InputArg> &Args, bool IsSoftFloat,
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CCState &State) {
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Function::const_arg_iterator FuncArg, CCState &State) {
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unsigned NumArgs = Args.size();
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unsigned CurArgIdx = 0;
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for (unsigned I = 0; I != NumArgs; ++I) {
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MVT ArgVT = Args[I].VT;
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ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
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std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx);
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CurArgIdx = Args[I].OrigArgIndex;
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if (!CC_Mips_FixedArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, State))
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if (ArgFlags.isByVal()) {
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handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, State);
|
||||
continue;
|
||||
}
|
||||
|
||||
MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), nullptr, IsSoftFloat);
|
||||
|
||||
if (!CC_Mips_FixedArg(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, State))
|
||||
continue;
|
||||
|
||||
#ifndef NDEBUG
|
||||
@ -3656,6 +3609,30 @@ void MipsTargetLowering::MipsCC::analyzeFormalArguments(
|
||||
}
|
||||
}
|
||||
|
||||
void MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
|
||||
MVT LocVT,
|
||||
CCValAssign::LocInfo LocInfo,
|
||||
ISD::ArgFlagsTy ArgFlags,
|
||||
CCState &State) {
|
||||
assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0.");
|
||||
|
||||
struct ByValArgInfo ByVal;
|
||||
unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
|
||||
unsigned ByValSize =
|
||||
RoundUpToAlignment(ArgFlags.getByValSize(), RegSizeInBytes);
|
||||
unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSizeInBytes),
|
||||
RegSizeInBytes * 2);
|
||||
|
||||
if (useRegsForByval())
|
||||
allocateRegs(ByVal, ByValSize, Align, State);
|
||||
|
||||
// Allocate space on caller's stack.
|
||||
unsigned Offset =
|
||||
State.AllocateStack(ByValSize - RegSizeInBytes * ByVal.NumRegs, Align);
|
||||
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
|
||||
ByValArgs.push_back(ByVal);
|
||||
}
|
||||
|
||||
unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
|
||||
return (Subtarget.isABI_O32() && (CallConv != CallingConv::Fast)) ? 16 : 0;
|
||||
}
|
||||
@ -3666,6 +3643,35 @@ const ArrayRef<MCPhysReg> MipsTargetLowering::MipsCC::intArgRegs() const {
|
||||
return makeArrayRef(Mips64IntRegs);
|
||||
}
|
||||
|
||||
const MCPhysReg *MipsTargetLowering::MipsCC::shadowRegs() const {
|
||||
return Subtarget.isABI_O32() ? O32IntRegs : Mips64DPRegs;
|
||||
}
|
||||
|
||||
void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
|
||||
unsigned ByValSize,
|
||||
unsigned Align, CCState &State) {
|
||||
unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
|
||||
const ArrayRef<MCPhysReg> IntArgRegs = intArgRegs();
|
||||
const MCPhysReg *ShadowRegs = shadowRegs();
|
||||
assert(!(ByValSize % RegSizeInBytes) && !(Align % RegSizeInBytes) &&
|
||||
"Byval argument's size and alignment should be a multiple of"
|
||||
"RegSizeInBytes.");
|
||||
|
||||
ByVal.FirstIdx =
|
||||
State.getFirstUnallocated(IntArgRegs.data(), IntArgRegs.size());
|
||||
|
||||
// If Align > RegSizeInBytes, the first arg register must be even.
|
||||
if ((Align > RegSizeInBytes) && (ByVal.FirstIdx % 2)) {
|
||||
State.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]);
|
||||
++ByVal.FirstIdx;
|
||||
}
|
||||
|
||||
// Mark the registers allocated.
|
||||
for (unsigned I = ByVal.FirstIdx; ByValSize && (I < IntArgRegs.size());
|
||||
ByValSize -= RegSizeInBytes, ++I, ++ByVal.NumRegs)
|
||||
State.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
|
||||
}
|
||||
|
||||
MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
|
||||
const SDNode *CallNode,
|
||||
bool IsSoftFloat) const {
|
||||
@ -3684,20 +3690,19 @@ MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy,
|
||||
void MipsTargetLowering::copyByValRegs(
|
||||
SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG,
|
||||
const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals,
|
||||
const Argument *FuncArg, const MipsCC &CC, unsigned FirstReg,
|
||||
unsigned LastReg, const CCValAssign &VA) const {
|
||||
const Argument *FuncArg, const MipsCC &CC, const ByValArgInfo &ByVal,
|
||||
const CCValAssign &VA) const {
|
||||
MachineFunction &MF = DAG.getMachineFunction();
|
||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||
unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
|
||||
unsigned NumRegs = LastReg - FirstReg;
|
||||
unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
|
||||
unsigned RegAreaSize = ByVal.NumRegs * GPRSizeInBytes;
|
||||
unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
|
||||
int FrameObjOffset;
|
||||
|
||||
if (RegAreaSize)
|
||||
FrameObjOffset =
|
||||
(int)CC.reservedArgArea() -
|
||||
(int)((CC.intArgRegs().size() - FirstReg) * GPRSizeInBytes);
|
||||
(int)((CC.intArgRegs().size() - ByVal.FirstIdx) * GPRSizeInBytes);
|
||||
else
|
||||
FrameObjOffset = VA.getLocMemOffset();
|
||||
|
||||
@ -3707,15 +3712,15 @@ void MipsTargetLowering::copyByValRegs(
|
||||
SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
|
||||
InVals.push_back(FIN);
|
||||
|
||||
if (!NumRegs)
|
||||
if (!ByVal.NumRegs)
|
||||
return;
|
||||
|
||||
// Copy arg registers.
|
||||
MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
|
||||
const TargetRegisterClass *RC = getRegClassFor(RegTy);
|
||||
|
||||
for (unsigned I = 0; I < NumRegs; ++I) {
|
||||
unsigned ArgReg = CC.intArgRegs()[FirstReg + I];
|
||||
for (unsigned I = 0; I < ByVal.NumRegs; ++I) {
|
||||
unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I];
|
||||
unsigned VReg = addLiveIn(MF, ArgReg, RC);
|
||||
unsigned Offset = I * GPRSizeInBytes;
|
||||
SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
|
||||
@ -3733,29 +3738,29 @@ void MipsTargetLowering::passByValArg(
|
||||
std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
|
||||
SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
|
||||
MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, const MipsCC &CC,
|
||||
unsigned FirstReg, unsigned LastReg, const ISD::ArgFlagsTy &Flags,
|
||||
bool isLittle, const CCValAssign &VA) const {
|
||||
const ByValArgInfo &ByVal, const ISD::ArgFlagsTy &Flags, bool isLittle,
|
||||
const CCValAssign &VA) const {
|
||||
unsigned ByValSizeInBytes = Flags.getByValSize();
|
||||
unsigned OffsetInBytes = 0; // From beginning of struct
|
||||
unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
|
||||
unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
|
||||
EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
|
||||
unsigned NumRegs = LastReg - FirstReg;
|
||||
|
||||
if (NumRegs) {
|
||||
if (ByVal.NumRegs) {
|
||||
const ArrayRef<MCPhysReg> ArgRegs = CC.intArgRegs();
|
||||
bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
|
||||
bool LeftoverBytes = (ByVal.NumRegs * RegSizeInBytes > ByValSizeInBytes);
|
||||
unsigned I = 0;
|
||||
|
||||
// Copy words to registers.
|
||||
for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
|
||||
for (; I < ByVal.NumRegs - LeftoverBytes;
|
||||
++I, OffsetInBytes += RegSizeInBytes) {
|
||||
SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
|
||||
DAG.getConstant(OffsetInBytes, PtrTy));
|
||||
SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
|
||||
MachinePointerInfo(), false, false, false,
|
||||
Alignment);
|
||||
MemOpChains.push_back(LoadVal.getValue(1));
|
||||
unsigned ArgReg = ArgRegs[FirstReg + I];
|
||||
unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
|
||||
RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
|
||||
}
|
||||
|
||||
@ -3765,6 +3770,9 @@ void MipsTargetLowering::passByValArg(
|
||||
|
||||
// Copy the remainder of the byval argument with sub-word loads and shifts.
|
||||
if (LeftoverBytes) {
|
||||
assert((ByValSizeInBytes > OffsetInBytes) &&
|
||||
(ByValSizeInBytes < OffsetInBytes + RegSizeInBytes) &&
|
||||
"Size of the remainder should be smaller than RegSizeInBytes.");
|
||||
SDValue Val;
|
||||
|
||||
for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
|
||||
@ -3804,7 +3812,7 @@ void MipsTargetLowering::passByValArg(
|
||||
Alignment = std::min(Alignment, LoadSizeInBytes);
|
||||
}
|
||||
|
||||
unsigned ArgReg = ArgRegs[FirstReg + I];
|
||||
unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I];
|
||||
RegsToPass.push_back(std::make_pair(ArgReg, Val));
|
||||
return;
|
||||
}
|
||||
@ -3867,49 +3875,3 @@ void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
|
||||
OutChains.push_back(Store);
|
||||
}
|
||||
}
|
||||
|
||||
void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
|
||||
unsigned Align) const {
|
||||
MachineFunction &MF = State->getMachineFunction();
|
||||
const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
|
||||
|
||||
assert(Size && "Byval argument's size shouldn't be 0.");
|
||||
|
||||
Align = std::min(Align, TFL->getStackAlignment());
|
||||
|
||||
unsigned FirstReg = 0;
|
||||
unsigned NumRegs = 0;
|
||||
|
||||
if (State->getCallingConv() != CallingConv::Fast) {
|
||||
unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
|
||||
const ArrayRef<MCPhysReg> IntArgRegs = Subtarget.getABI().GetByValArgRegs();
|
||||
// FIXME: The O32 case actually describes no shadow registers.
|
||||
const MCPhysReg *ShadowRegs =
|
||||
Subtarget.isABI_O32() ? IntArgRegs.data() : Mips64DPRegs;
|
||||
|
||||
// We used to check the size as well but we can't do that anymore since
|
||||
// CCState::HandleByVal() rounds up the size after calling this function.
|
||||
assert(!(Align % RegSizeInBytes) &&
|
||||
"Byval argument's alignment should be a multiple of"
|
||||
"RegSizeInBytes.");
|
||||
|
||||
FirstReg = State->getFirstUnallocated(IntArgRegs.data(), IntArgRegs.size());
|
||||
|
||||
// If Align > RegSizeInBytes, the first arg register must be even.
|
||||
// FIXME: This condition happens to do the right thing but it's not the
|
||||
// right way to test it. We want to check that the stack frame offset
|
||||
// of the register is aligned.
|
||||
if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
|
||||
State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
|
||||
++FirstReg;
|
||||
}
|
||||
|
||||
// Mark the registers allocated.
|
||||
Size = RoundUpToAlignment(Size, RegSizeInBytes);
|
||||
for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
|
||||
Size -= RegSizeInBytes, ++I, ++NumRegs)
|
||||
State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
|
||||
}
|
||||
|
||||
State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
|
||||
}
|
||||
|
@ -259,8 +259,6 @@ namespace llvm {
|
||||
}
|
||||
};
|
||||
|
||||
void HandleByVal(CCState *, unsigned &, unsigned) const override;
|
||||
|
||||
protected:
|
||||
SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
|
||||
|
||||
@ -341,6 +339,14 @@ namespace llvm {
|
||||
bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
|
||||
SDValue Chain) const;
|
||||
|
||||
/// ByValArgInfo - Byval argument information.
|
||||
struct ByValArgInfo {
|
||||
unsigned FirstIdx; // Index of the first register used.
|
||||
unsigned NumRegs; // Number of registers used for this argument.
|
||||
|
||||
ByValArgInfo() : FirstIdx(0), NumRegs(0) {}
|
||||
};
|
||||
|
||||
/// MipsCC - This class provides methods used to analyze formal and call
|
||||
/// arguments and inquire about calling convention information.
|
||||
class MipsCC {
|
||||
@ -359,8 +365,12 @@ namespace llvm {
|
||||
CCState &State);
|
||||
void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
bool IsSoftFloat,
|
||||
Function::const_arg_iterator FuncArg,
|
||||
CCState &State);
|
||||
|
||||
/// hasByValArg - Returns true if function has byval arguments.
|
||||
bool hasByValArg() const { return !ByValArgs.empty(); }
|
||||
|
||||
/// reservedArgArea - The size of the area the caller reserves for
|
||||
/// register arguments. This is 16-byte if ABI is O32.
|
||||
unsigned reservedArgArea() const;
|
||||
@ -368,7 +378,24 @@ namespace llvm {
|
||||
/// Return pointer to array of integer argument registers.
|
||||
const ArrayRef<MCPhysReg> intArgRegs() const;
|
||||
|
||||
typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
|
||||
byval_iterator byval_begin() const { return ByValArgs.begin(); }
|
||||
byval_iterator byval_end() const { return ByValArgs.end(); }
|
||||
|
||||
private:
|
||||
void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
|
||||
CCValAssign::LocInfo LocInfo,
|
||||
ISD::ArgFlagsTy ArgFlags, CCState &State);
|
||||
|
||||
/// useRegsForByval - Returns true if the calling convention allows the
|
||||
/// use of registers to pass byval arguments.
|
||||
bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
|
||||
|
||||
const MCPhysReg *shadowRegs() const;
|
||||
|
||||
void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, unsigned Align,
|
||||
CCState &State);
|
||||
|
||||
/// Return the type of the register which is used to pass an argument or
|
||||
/// return a value. This function returns f64 if the argument is an i64
|
||||
/// value which has been generated as a result of softening an f128 value.
|
||||
@ -384,6 +411,7 @@ namespace llvm {
|
||||
|
||||
CallingConv::ID CallConv;
|
||||
const MipsSubtarget &Subtarget;
|
||||
SmallVector<ByValArgInfo, 2> ByValArgs;
|
||||
};
|
||||
protected:
|
||||
SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
|
||||
@ -448,9 +476,9 @@ namespace llvm {
|
||||
/// isEligibleForTailCallOptimization - Check whether the call is eligible
|
||||
/// for tail call optimization.
|
||||
virtual bool
|
||||
isEligibleForTailCallOptimization(const CCState &CCInfo,
|
||||
isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
|
||||
unsigned NextStackOffset,
|
||||
const MipsFunctionInfo &FI) const = 0;
|
||||
const MipsFunctionInfo& FI) const = 0;
|
||||
|
||||
/// copyByValArg - Copy argument registers which were used to pass a byval
|
||||
/// argument to the stack. Create a stack frame object for the byval
|
||||
@ -459,15 +487,14 @@ namespace llvm {
|
||||
SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
|
||||
SmallVectorImpl<SDValue> &InVals,
|
||||
const Argument *FuncArg, const MipsCC &CC,
|
||||
unsigned FirstReg, unsigned LastReg,
|
||||
const CCValAssign &VA) const;
|
||||
const ByValArgInfo &ByVal, const CCValAssign &VA) const;
|
||||
|
||||
/// passByValArg - Pass a byval argument in registers or on stack.
|
||||
void passByValArg(SDValue Chain, SDLoc DL,
|
||||
std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
|
||||
SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
|
||||
MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
|
||||
const MipsCC &CC, unsigned FirstReg, unsigned LastReg,
|
||||
const MipsCC &CC, const ByValArgInfo &ByVal,
|
||||
const ISD::ArgFlagsTy &Flags, bool isLittle,
|
||||
const CCValAssign &VA) const;
|
||||
|
||||
|
@ -1167,14 +1167,15 @@ MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
||||
}
|
||||
}
|
||||
|
||||
bool MipsSETargetLowering::isEligibleForTailCallOptimization(
|
||||
const CCState &CCInfo, unsigned NextStackOffset,
|
||||
const MipsFunctionInfo &FI) const {
|
||||
bool MipsSETargetLowering::
|
||||
isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
|
||||
unsigned NextStackOffset,
|
||||
const MipsFunctionInfo& FI) const {
|
||||
if (!EnableMipsTailCalls)
|
||||
return false;
|
||||
|
||||
// Return false if either the callee or caller has a byval argument.
|
||||
if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
|
||||
if (MipsCCInfo.hasByValArg() || FI.hasByvalArg())
|
||||
return false;
|
||||
|
||||
// Return true if the callee's argument area is no larger than the
|
||||
|
@ -51,9 +51,9 @@ namespace llvm {
|
||||
const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
|
||||
|
||||
private:
|
||||
bool isEligibleForTailCallOptimization(
|
||||
const CCState &CCInfo, unsigned NextStackOffset,
|
||||
const MipsFunctionInfo &FI) const override;
|
||||
bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
|
||||
unsigned NextStackOffset,
|
||||
const MipsFunctionInfo& FI) const override;
|
||||
|
||||
void
|
||||
getOpndList(SmallVectorImpl<SDValue> &Ops,
|
||||
|
Loading…
Reference in New Issue
Block a user