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https://github.com/c64scene-ar/llvm-6502.git
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Stop using MCSectionData in MCMachObjectWriter.h.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238165 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -21,7 +21,6 @@
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namespace llvm {
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class MCSectionData;
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class MachObjectWriter;
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class MCMachObjectTargetWriter {
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@ -102,8 +101,8 @@ class MachObjectWriter : public MCObjectWriter {
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: Sym(Sym), MRE(MRE) {}
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};
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llvm::DenseMap<const MCSectionData *, std::vector<RelAndSymbol>> Relocations;
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llvm::DenseMap<const MCSectionData*, unsigned> IndirectSymBase;
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llvm::DenseMap<const MCSection *, std::vector<RelAndSymbol>> Relocations;
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llvm::DenseMap<const MCSection *, unsigned> IndirectSymBase;
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/// @}
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/// \name Symbol Table Data
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@ -149,8 +148,7 @@ public:
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uint64_t getFragmentAddress(const MCFragment *Fragment,
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const MCAsmLayout &Layout) const;
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uint64_t getPaddingSize(const MCSectionData *SD,
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const MCAsmLayout &Layout) const;
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uint64_t getPaddingSize(const MCSection *SD, const MCAsmLayout &Layout) const;
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bool doesSymbolRequireExternRelocation(const MCSymbol &S);
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@ -180,7 +178,7 @@ public:
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uint64_t SectionDataSize);
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void WriteSection(const MCAssembler &Asm, const MCAsmLayout &Layout,
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const MCSectionData &SD, uint64_t FileOffset,
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const MCSection &Sec, uint64_t FileOffset,
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uint64_t RelocationsStart, unsigned NumRelocations);
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void WriteSymtabLoadCommand(uint32_t SymbolOffset, uint32_t NumSymbols,
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@ -222,10 +220,10 @@ public:
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// to a symbol it should be passed as \p RelSymbol so that it can be updated
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// afterwards. If the relocation doesn't refer to a symbol, nullptr should be
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// used.
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void addRelocation(const MCSymbol *RelSymbol, const MCSectionData *SD,
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void addRelocation(const MCSymbol *RelSymbol, const MCSection *Sec,
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MachO::any_relocation_info &MRE) {
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RelAndSymbol P(RelSymbol, MRE);
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Relocations[SD].push_back(P);
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Relocations[Sec].push_back(P);
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}
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void RecordScatteredRelocation(const MCAssembler &Asm,
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@ -105,11 +105,11 @@ uint64_t MachObjectWriter::getSymbolAddress(const MCSymbol &S,
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Layout.getSymbolOffset(S);
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}
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uint64_t MachObjectWriter::getPaddingSize(const MCSectionData *SD,
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uint64_t MachObjectWriter::getPaddingSize(const MCSection *Sec,
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const MCAsmLayout &Layout) const {
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uint64_t EndAddr =
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getSectionAddress(&SD->getSection()) + Layout.getSectionAddressSize(SD);
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unsigned Next = SD->getSection().getLayoutOrder() + 1;
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uint64_t EndAddr = getSectionAddress(Sec) +
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Layout.getSectionAddressSize(&Sec->getSectionData());
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unsigned Next = Sec->getLayoutOrder() + 1;
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if (Next >= Layout.getSectionOrder().size())
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return 0;
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@ -195,12 +195,12 @@ void MachObjectWriter::WriteSegmentLoadCommand(unsigned NumSections,
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void MachObjectWriter::WriteSection(const MCAssembler &Asm,
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const MCAsmLayout &Layout,
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const MCSectionData &SD,
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uint64_t FileOffset,
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const MCSection &Sec, uint64_t FileOffset,
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uint64_t RelocationsStart,
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unsigned NumRelocations) {
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const MCSectionData &SD = Sec.getSectionData();
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uint64_t SectionSize = Layout.getSectionAddressSize(&SD);
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const MCSectionMachO &Section = cast<MCSectionMachO>(SD.getSection());
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const MCSectionMachO &Section = cast<MCSectionMachO>(Sec);
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// The offset is unused for virtual sections.
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if (Section.isVirtualSection()) {
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@ -234,7 +234,7 @@ void MachObjectWriter::WriteSection(const MCAssembler &Asm,
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Write32(NumRelocations ? RelocationsStart : 0);
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Write32(NumRelocations);
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Write32(Flags);
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Write32(IndirectSymBase.lookup(&SD)); // reserved1
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Write32(IndirectSymBase.lookup(&SD.getSection())); // reserved1
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Write32(Section.getStubSize()); // reserved2
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if (is64Bit())
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Write32(0); // reserved3
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@ -502,7 +502,8 @@ void MachObjectWriter::BindIndirectSymbols(MCAssembler &Asm) {
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continue;
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// Initialize the section indirect symbol base, if necessary.
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IndirectSymBase.insert(std::make_pair(it->SectionData, IndirectIndex));
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IndirectSymBase.insert(
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std::make_pair(&it->SectionData->getSection(), IndirectIndex));
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Asm.getOrCreateSymbolData(*it->Symbol);
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}
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@ -519,7 +520,8 @@ void MachObjectWriter::BindIndirectSymbols(MCAssembler &Asm) {
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continue;
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// Initialize the section indirect symbol base, if necessary.
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IndirectSymBase.insert(std::make_pair(it->SectionData, IndirectIndex));
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IndirectSymBase.insert(
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std::make_pair(&it->SectionData->getSection(), IndirectIndex));
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// Set the symbol type to undefined lazy, but only on construction.
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//
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@ -624,8 +626,7 @@ void MachObjectWriter::ComputeSymbolTable(
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UndefinedSymbolData[i].Symbol->setIndex(Index++);
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for (const MCSection &Section : Asm) {
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const MCSectionData &SD = Section.getSectionData();
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std::vector<RelAndSymbol> &Relocs = Relocations[&SD];
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std::vector<RelAndSymbol> &Relocs = Relocations[&Section];
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for (RelAndSymbol &Rel : Relocs) {
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if (!Rel.Sym)
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continue;
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@ -655,7 +656,7 @@ void MachObjectWriter::computeSectionAddresses(const MCAssembler &Asm,
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// Explicitly pad the section to match the alignment requirements of the
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// following one. This is for 'gas' compatibility, it shouldn't
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/// strictly be necessary.
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StartAddress += getPaddingSize(SD, Layout);
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StartAddress += getPaddingSize(&SD->getSection(), Layout);
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}
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}
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@ -807,7 +808,7 @@ void MachObjectWriter::WriteObject(MCAssembler &Asm,
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uint64_t Address = getSectionAddress(&*it);
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uint64_t Size = Layout.getSectionAddressSize(&SD);
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uint64_t FileSize = Layout.getSectionFileSize(&SD);
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FileSize += getPaddingSize(&SD, Layout);
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FileSize += getPaddingSize(&*it, Layout);
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VMSize = std::max(VMSize, Address + Size);
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@ -834,11 +835,10 @@ void MachObjectWriter::WriteObject(MCAssembler &Asm,
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uint64_t RelocTableEnd = SectionDataStart + SectionDataFileSize;
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for (MCAssembler::const_iterator it = Asm.begin(),
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ie = Asm.end(); it != ie; ++it) {
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const MCSectionData &SD = it->getSectionData();
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std::vector<RelAndSymbol> &Relocs = Relocations[&SD];
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std::vector<RelAndSymbol> &Relocs = Relocations[&*it];
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unsigned NumRelocs = Relocs.size();
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uint64_t SectionStart = SectionDataStart + getSectionAddress(&*it);
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WriteSection(Asm, Layout, SD, SectionStart, RelocTableEnd, NumRelocs);
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WriteSection(Asm, Layout, *it, SectionStart, RelocTableEnd, NumRelocs);
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RelocTableEnd += NumRelocs * sizeof(MachO::any_relocation_info);
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}
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@ -917,7 +917,7 @@ void MachObjectWriter::WriteObject(MCAssembler &Asm,
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const MCSectionData &SD = it->getSectionData();
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Asm.writeSectionData(&SD, Layout);
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uint64_t Pad = getPaddingSize(&SD, Layout);
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uint64_t Pad = getPaddingSize(&*it, Layout);
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WriteZeros(Pad);
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}
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@ -929,7 +929,7 @@ void MachObjectWriter::WriteObject(MCAssembler &Asm,
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ie = Asm.end(); it != ie; ++it) {
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// Write the section relocation entries, in reverse order to match 'as'
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// (approximately, the exact algorithm is more complicated than this).
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std::vector<RelAndSymbol> &Relocs = Relocations[&it->getSectionData()];
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std::vector<RelAndSymbol> &Relocs = Relocations[&*it];
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for (unsigned i = 0, e = Relocs.size(); i != e; ++i) {
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Write32(Relocs[e - i - 1].MRE.r_word0);
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Write32(Relocs[e - i - 1].MRE.r_word1);
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@ -229,8 +229,7 @@ void AArch64MachObjectWriter::RecordRelocation(
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MachO::any_relocation_info MRE;
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MRE.r_word0 = FixupOffset;
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MRE.r_word1 = (IsPCRel << 24) | (Log2Size << 25) | (Type << 28);
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Writer->addRelocation(A_Base, &Fragment->getParent()->getSectionData(),
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MRE);
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Writer->addRelocation(A_Base, Fragment->getParent(), MRE);
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return;
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} else if (Target.getSymA()->getKind() != MCSymbolRefExpr::VK_None ||
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Target.getSymB()->getKind() != MCSymbolRefExpr::VK_None)
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@ -279,8 +278,7 @@ void AArch64MachObjectWriter::RecordRelocation(
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MachO::any_relocation_info MRE;
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MRE.r_word0 = FixupOffset;
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MRE.r_word1 = (IsPCRel << 24) | (Log2Size << 25) | (Type << 28);
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Writer->addRelocation(A_Base, &Fragment->getParent()->getSectionData(),
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MRE);
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Writer->addRelocation(A_Base, Fragment->getParent(), MRE);
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RelSymbol = B_Base;
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Type = MachO::ARM64_RELOC_SUBTRACTOR;
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@ -387,8 +385,7 @@ void AArch64MachObjectWriter::RecordRelocation(
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MRE.r_word0 = FixupOffset;
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MRE.r_word1 =
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(Index << 0) | (IsPCRel << 24) | (Log2Size << 25) | (Type << 28);
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Writer->addRelocation(RelSymbol, &Fragment->getParent()->getSectionData(),
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MRE);
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Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE);
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// Now set up the Addend relocation.
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Type = MachO::ARM64_RELOC_ADDEND;
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@ -409,8 +406,7 @@ void AArch64MachObjectWriter::RecordRelocation(
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MRE.r_word0 = FixupOffset;
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MRE.r_word1 =
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(Index << 0) | (IsPCRel << 24) | (Log2Size << 25) | (Type << 28);
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Writer->addRelocation(RelSymbol, &Fragment->getParent()->getSectionData(),
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MRE);
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Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE);
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}
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MCObjectWriter *llvm::createAArch64MachObjectWriter(raw_pwrite_stream &OS,
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@ -227,8 +227,7 @@ RecordARMScatteredHalfRelocation(MachObjectWriter *Writer,
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(IsPCRel << 30) |
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MachO::R_SCATTERED);
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MRE.r_word1 = Value2;
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Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(),
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MRE);
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Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
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}
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MachO::any_relocation_info MRE;
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@ -239,7 +238,7 @@ RecordARMScatteredHalfRelocation(MachObjectWriter *Writer,
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(IsPCRel << 30) |
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MachO::R_SCATTERED);
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MRE.r_word1 = Value;
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Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(), MRE);
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Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
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}
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void ARMMachObjectWriter::RecordARMScatteredRelocation(MachObjectWriter *Writer,
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@ -294,8 +293,7 @@ void ARMMachObjectWriter::RecordARMScatteredRelocation(MachObjectWriter *Writer,
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(IsPCRel << 30) |
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MachO::R_SCATTERED);
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MRE.r_word1 = Value2;
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Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(),
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MRE);
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Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
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}
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MachO::any_relocation_info MRE;
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@ -305,7 +303,7 @@ void ARMMachObjectWriter::RecordARMScatteredRelocation(MachObjectWriter *Writer,
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(IsPCRel << 30) |
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MachO::R_SCATTERED);
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MRE.r_word1 = Value;
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Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(), MRE);
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Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
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}
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bool ARMMachObjectWriter::requiresExternRelocation(MachObjectWriter *Writer,
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@ -466,12 +464,10 @@ void ARMMachObjectWriter::RecordRelocation(MachObjectWriter *Writer,
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(Log2Size << 25) |
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(MachO::ARM_RELOC_PAIR << 28));
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Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(),
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MREPair);
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Writer->addRelocation(nullptr, Fragment->getParent(), MREPair);
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}
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Writer->addRelocation(RelSymbol, &Fragment->getParent()->getSectionData(),
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MRE);
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Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE);
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}
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MCObjectWriter *llvm::createARMMachObjectWriter(raw_pwrite_stream &OS,
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@ -282,8 +282,7 @@ bool PPCMachObjectWriter::RecordScatteredRelocation(
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MachO::any_relocation_info MRE;
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makeScatteredRelocationInfo(MRE, other_half, MachO::GENERIC_RELOC_PAIR,
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Log2Size, IsPCRel, Value2);
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Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(),
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MRE);
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Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
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} else {
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// If the offset is more than 24-bits, it won't fit in a scattered
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// relocation offset field, so we fall back to using a non-scattered
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@ -297,7 +296,7 @@ bool PPCMachObjectWriter::RecordScatteredRelocation(
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}
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MachO::any_relocation_info MRE;
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makeScatteredRelocationInfo(MRE, FixupOffset, Type, Log2Size, IsPCRel, Value);
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Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(), MRE);
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Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
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return true;
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}
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@ -375,8 +374,7 @@ void PPCMachObjectWriter::RecordPPCRelocation(
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// struct relocation_info (8 bytes)
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MachO::any_relocation_info MRE;
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makeRelocationInfo(MRE, FixupOffset, Index, IsPCRel, Log2Size, false, Type);
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Writer->addRelocation(RelSymbol, &Fragment->getParent()->getSectionData(),
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MRE);
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Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE);
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}
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MCObjectWriter *llvm::createPPCMachObjectWriter(raw_pwrite_stream &OS,
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@ -197,8 +197,7 @@ void X86MachObjectWriter::RecordX86_64Relocation(
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MRE.r_word0 = FixupOffset;
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MRE.r_word1 =
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(Index << 0) | (IsPCRel << 24) | (Log2Size << 25) | (Type << 28);
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Writer->addRelocation(A_Base, &Fragment->getParent()->getSectionData(),
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MRE);
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Writer->addRelocation(A_Base, Fragment->getParent(), MRE);
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if (B_Base)
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RelSymbol = B_Base;
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@ -337,8 +336,7 @@ void X86MachObjectWriter::RecordX86_64Relocation(
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MRE.r_word0 = FixupOffset;
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MRE.r_word1 = (Index << 0) | (IsPCRel << 24) | (Log2Size << 25) |
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(IsExtern << 27) | (Type << 28);
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Writer->addRelocation(RelSymbol, &Fragment->getParent()->getSectionData(),
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MRE);
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Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE);
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}
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bool X86MachObjectWriter::RecordScatteredRelocation(MachObjectWriter *Writer,
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@ -411,8 +409,7 @@ bool X86MachObjectWriter::RecordScatteredRelocation(MachObjectWriter *Writer,
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(IsPCRel << 30) |
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MachO::R_SCATTERED);
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MRE.r_word1 = Value2;
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Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(),
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MRE);
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Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
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} else {
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// If the offset is more than 24-bits, it won't fit in a scattered
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// relocation offset field, so we fall back to using a non-scattered
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@ -434,7 +431,7 @@ bool X86MachObjectWriter::RecordScatteredRelocation(MachObjectWriter *Writer,
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(IsPCRel << 30) |
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MachO::R_SCATTERED);
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MRE.r_word1 = Value;
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Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(), MRE);
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Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
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return true;
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}
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@ -476,8 +473,8 @@ void X86MachObjectWriter::RecordTLVPRelocation(MachObjectWriter *Writer,
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MRE.r_word0 = Value;
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MRE.r_word1 =
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(IsPCRel << 24) | (Log2Size << 25) | (MachO::GENERIC_RELOC_TLV << 28);
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Writer->addRelocation(&Target.getSymA()->getSymbol(),
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&Fragment->getParent()->getSectionData(), MRE);
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Writer->addRelocation(&Target.getSymA()->getSymbol(), Fragment->getParent(),
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MRE);
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}
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void X86MachObjectWriter::RecordX86Relocation(MachObjectWriter *Writer,
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@ -573,8 +570,7 @@ void X86MachObjectWriter::RecordX86Relocation(MachObjectWriter *Writer,
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MRE.r_word0 = FixupOffset;
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MRE.r_word1 =
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(Index << 0) | (IsPCRel << 24) | (Log2Size << 25) | (Type << 28);
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Writer->addRelocation(RelSymbol, &Fragment->getParent()->getSectionData(),
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MRE);
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Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE);
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}
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MCObjectWriter *llvm::createX86MachObjectWriter(raw_pwrite_stream &OS,
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