From 184c0f8b2f6dfcca8137b019190fef52a3ff10e2 Mon Sep 17 00:00:00 2001
From: Quentin Colombet <qcolombet@apple.com>
Date: Mon, 18 Aug 2014 17:55:21 +0000
Subject: [PATCH] [X86][Haswell][SchedModel] Add architecture specific
 scheduling models. Group: Integer instructions. Sub-group: Synchronization
 instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215909 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86SchedHaswell.td | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/lib/Target/X86/X86SchedHaswell.td b/lib/Target/X86/X86SchedHaswell.td
index cc4cd90c6f6..2f78f62809c 100644
--- a/lib/Target/X86/X86SchedHaswell.td
+++ b/lib/Target/X86/X86SchedHaswell.td
@@ -916,4 +916,30 @@ def WriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
 }
 def : InstRW<[WriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
 
+//-- Synchronization instructions --//
+
+// XADD.
+def WriteXADD : SchedWriteRes<[]> {
+  let NumMicroOps = 5;
+}
+def : InstRW<[WriteXADD], (instregex "XADD(8|16|32|64)rm")>;
+
+// CMPXCHG.
+def WriteCMPXCHG : SchedWriteRes<[]> {
+  let NumMicroOps = 6;
+}
+def : InstRW<[WriteCMPXCHG], (instregex "CMPXCHG(8|16|32|64)rm")>;
+
+// CMPXCHG8B.
+def WriteCMPXCHG8B : SchedWriteRes<[]> {
+  let NumMicroOps = 15;
+}
+def : InstRW<[WriteCMPXCHG8B], (instregex "CMPXCHG8B")>;
+
+// CMPXCHG16B.
+def WriteCMPXCHG16B : SchedWriteRes<[]> {
+  let NumMicroOps = 22;
+}
+def : InstRW<[WriteCMPXCHG16B], (instregex "CMPXCHG16B")>;
+
 } // SchedModel