mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-20 10:30:03 +00:00
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
7abddda6cc
commit
1877ec9b02
@ -196,8 +196,65 @@ void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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CodeGenMap.clear();
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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// Check to see if this function uses vector registers, which means we have to
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// save and restore the VRSAVE register and update it with the regs we use.
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//
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// In this case, there will be virtual registers of vector type type created
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// by the scheduler. Detect them now.
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SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
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bool HasVectorVReg = false;
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for (unsigned i = MRegisterInfo::FirstVirtualRegister,
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e = RegMap->getLastVirtReg(); i != e; ++i)
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if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) {
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HasVectorVReg = true;
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break;
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}
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// If we have a vector register, we want to emit code into the entry and exit
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// blocks to save and restore the VRSAVE register. We do this here (instead
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// of marking all vector instructions as clobbering VRSAVE) for two reasons:
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//
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// 1. This (trivially) reduces the load on the register allocator, by not
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// having to represent the live range of the VRSAVE register.
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// 2. This (more significantly) allows us to create a temporary virtual
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// register to hold the saved VRSAVE value, allowing this temporary to be
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// register allocated, instead of forcing it to be spilled to the stack.
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if (HasVectorVReg) {
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// Create two vregs - one to hold the VRSAVE register that is live-in to the
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// function and one for the value after having bits or'd into it.
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unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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MachineFunction &MF = DAG.getMachineFunction();
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MachineBasicBlock &EntryBB = *MF.begin();
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// Emit the following code into the entry block:
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// InVRSAVE = MFVRSAVE
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// UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
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// MTVRSAVE UpdatedVRSAVE
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MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
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BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE);
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BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE);
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BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE);
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// Find all return blocks, outputting a restore in each epilog.
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const TargetInstrInfo &TII = *DAG.getTarget().getInstrInfo();
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for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
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if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
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IP = BB->end(); --IP;
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// Skip over all terminator instructions, which are part of the return
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// sequence.
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MachineBasicBlock::iterator I2 = IP;
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while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
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IP = I2;
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// Emit: MTVRSAVE InVRSave
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BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE);
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}
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}
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}
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/// getGlobalBaseReg - Output the instructions required to put the
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@ -210,6 +210,9 @@ def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
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def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
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"; ADJCALLSTACKUP",
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[(callseq_end imm:$amt)]>;
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def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
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"UPDATE_VRSAVE $rD, $rS", []>;
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}
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def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
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[(set GPRC:$rD, (undef))]>;
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@ -694,8 +697,24 @@ def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
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//
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def MFCTR : XFXForm_1_ext<31, 339, 9, (ops GPRC:$rT), "mfctr $rT", SprMFSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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def MFLR : XFXForm_1_ext<31, 339, 8, (ops GPRC:$rT), "mflr $rT", SprMFSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
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// a GPR on the PPC970. As such, copies in and out have the same performance
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// characteristics as an OR instruction.
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def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS),
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"mtspr 256, $rS", IntGeneral>,
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PPC970_Unit_FXU;
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def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (ops GPRC:$rT),
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"mfspr $rT, 256", IntGeneral>,
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PPC970_Unit_FXU;
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def MFCR : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT", SprMFCR>,
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PPC970_MicroCode, PPC970_Unit_CRU;
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def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
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@ -704,13 +723,6 @@ def MTCRF : XFXForm_5<31, 144, (ops crbitm:$FXM, GPRC:$rS),
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def MFOCRF: XFXForm_5a<31, 19, (ops GPRC:$rT, crbitm:$FXM),
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"mfcr $rT, $FXM", SprMFCR>,
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PPC970_DGroup_First, PPC970_Unit_CRU;
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def MTCTR : XFXForm_7_ext<31, 467, 9, (ops GPRC:$rS), "mtctr $rS", SprMTSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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def MTLR : XFXForm_7_ext<31, 467, 8, (ops GPRC:$rS), "mtlr $rS", SprMTSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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def MTSPR : XFXForm_7<31, 467, (ops GPRC:$rS, u16imm:$UIMM), "mtspr $UIMM, $rS",
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SprMTSPR>,
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PPC970_DGroup_Single, PPC970_Unit_FXU;
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// XS-Form instructions. Just 'sradi'
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//
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@ -266,12 +266,63 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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}
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}
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// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
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// instruction selector. Based on the vector registers that have been used,
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// transform this into the appropriate ORI instruction.
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static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
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unsigned UsedRegMask = 0;
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#define HANDLEREG(N) if (UsedRegs[PPC::V##N]) UsedRegMask |= 1 << (31-N)
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HANDLEREG( 0); HANDLEREG( 1); HANDLEREG( 2); HANDLEREG( 3);
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HANDLEREG( 4); HANDLEREG( 5); HANDLEREG( 6); HANDLEREG( 7);
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HANDLEREG( 8); HANDLEREG( 9); HANDLEREG(10); HANDLEREG(11);
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HANDLEREG(12); HANDLEREG(13); HANDLEREG(14); HANDLEREG(15);
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HANDLEREG(16); HANDLEREG(17); HANDLEREG(18); HANDLEREG(19);
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HANDLEREG(20); HANDLEREG(21); HANDLEREG(22); HANDLEREG(23);
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HANDLEREG(24); HANDLEREG(25); HANDLEREG(26); HANDLEREG(27);
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HANDLEREG(28); HANDLEREG(29); HANDLEREG(30); HANDLEREG(31);
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#undef HANDLEREG
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unsigned SrcReg = MI->getOperand(1).getReg();
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unsigned DstReg = MI->getOperand(0).getReg();
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// If no registers are used, turn this into a copy.
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if (UsedRegMask == 0) {
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if (SrcReg != DstReg)
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BuildMI(*MI->getParent(), MI, PPC::OR4, 2, DstReg)
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.addReg(SrcReg).addReg(SrcReg);
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} else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
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BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
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.addReg(SrcReg).addImm(UsedRegMask);
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} else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
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BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
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.addReg(SrcReg).addImm(UsedRegMask >> 16);
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} else {
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BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
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.addReg(SrcReg).addImm(UsedRegMask >> 16);
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BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
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.addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
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}
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// Remove the old UPDATE_VRSAVE instruction.
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MI->getParent()->erase(MI);
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}
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void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Scan the first few instructions of the prolog, looking for an UPDATE_VRSAVE
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// instruction. If we find it, process it.
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for (unsigned i = 0; MBBI != MBB.end() && i < 5; ++i, ++MBBI) {
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if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
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HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
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break;
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}
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}
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// Move MBBI back to the beginning of the function.
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MBBI = MBB.begin();
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// Get the number of bytes to allocate from the FrameInfo
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unsigned NumBytes = MFI->getStackSize();
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@ -152,9 +152,9 @@ def GPRC : RegisterClass<"PPC", [i32], 32,
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GPRCClass::iterator
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GPRCClass::allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF))
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return end()-4;
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return end()-4; // don't allocate R31, R0, R1, LR
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else
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return end()-3;
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return end()-3; // don't allocate R0, R1, LR
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}
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}];
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}
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