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[mips] Teach the delay slot filler to remove needless KILL instructions.

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Summary:
Previously, the presence of KILL instructions would block valid candidates
from filling a specific delay slot. With the elimination of the KILL
instructions, in the appropriate range, we are able to fill more slots and
keep the information from future def/use analysis consistent.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: hfinkel, llvm-commits

Differential Revision: http://reviews.llvm.org/D7724

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235183 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vasileios Kalintiris 2015-04-17 12:01:02 +00:00
parent c59decb902
commit 187afcd548
2 changed files with 44 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
lib/Target/Mips/MipsDelaySlotFiller.cpp
View File

@ -643,18 +643,34 @@ template<typename IterTy>
bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
RegDefsUses &RegDU, InspectMemInstr& IM, Iter Slot, RegDefsUses &RegDU, InspectMemInstr& IM, Iter Slot,
IterTy &Filler) const { IterTy &Filler) const {
for (IterTy I = Begin; I != End; ++I) { bool IsReverseIter = std::is_convertible<IterTy, ReverseIter>::value;
for (IterTy I = Begin; I != End;) {
IterTy CurrI = I;
++I;
// skip debug value // skip debug value
if (I->isDebugValue()) if (CurrI->isDebugValue())
continue; continue;
if (terminateSearch(*I)) if (terminateSearch(*CurrI))
break; break;
assert((!I->isCall() && !I->isReturn() && !I->isBranch()) && assert((!CurrI->isCall() && !CurrI->isReturn() && !CurrI->isBranch()) &&
"Cannot put calls, returns or branches in delay slot."); "Cannot put calls, returns or branches in delay slot.");
if (delayHasHazard(*I, RegDU, IM)) if (CurrI->isKill()) {
CurrI->eraseFromParent();
// This special case is needed for reverse iterators, because when we
// erase an instruction, the iterators are updated to point to the next
// instruction.
if (IsReverseIter && I != End)
I = CurrI;
continue;
}
if (delayHasHazard(*CurrI, RegDU, IM))
continue; continue;
const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>(); const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
@ -664,21 +680,21 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
// branches are not checked because non-NaCl targets never put them in // branches are not checked because non-NaCl targets never put them in
// delay slots. // delay slots.
unsigned AddrIdx; unsigned AddrIdx;
if ((isBasePlusOffsetMemoryAccess(I->getOpcode(), &AddrIdx) && if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) &&
baseRegNeedsLoadStoreMask(I->getOperand(AddrIdx).getReg())) || baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) ||
I->modifiesRegister(Mips::SP, STI.getRegisterInfo())) CurrI->modifiesRegister(Mips::SP, STI.getRegisterInfo()))
continue; continue;
} }
bool InMicroMipsMode = STI.inMicroMipsMode(); bool InMicroMipsMode = STI.inMicroMipsMode();
const MipsInstrInfo *TII = STI.getInstrInfo(); const MipsInstrInfo *TII = STI.getInstrInfo();
unsigned Opcode = (*Slot).getOpcode(); unsigned Opcode = (*Slot).getOpcode();
if (InMicroMipsMode && TII->GetInstSizeInBytes(&(*I)) == 2 && if (InMicroMipsMode && TII->GetInstSizeInBytes(&(*CurrI)) == 2 &&
(Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch || (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch ||
Opcode == Mips::PseudoReturn)) Opcode == Mips::PseudoReturn))
continue; continue;
Filler = I; Filler = CurrI;
return true; return true;
} }
@ -843,7 +859,10 @@ bool Filler::examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ,
bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU, bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU,
InspectMemInstr &IM) const { InspectMemInstr &IM) const {
bool HasHazard = (Candidate.isImplicitDef() || Candidate.isKill()); assert(!Candidate.isKill() &&
"KILL instructions should have been eliminated at this point.");
bool HasHazard = Candidate.isImplicitDef();
HasHazard |= IM.hasHazard(Candidate); HasHazard |= IM.hasHazard(Candidate);
HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands()); HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands());

14
test/CodeGen/Mips/delay-slot-kill.ll Normal file
View File

@ -0,0 +1,14 @@
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s
; Currently, the following IR assembly generates a KILL instruction between
; the bitwise-and instruction and the return instruction. We verify that the
; delay slot filler ignores such KILL instructions by filling the slot of the
; return instruction properly.
define signext i32 @f1(i32 signext %a, i32 signext %b) {
entry:
; CHECK: jr $ra
; CHECK-NEXT: and $2, $4, $5
%r = and i32 %a, %b
ret i32 %r
}